Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
181 words
Digital data apparatus comprising a data processing unit and a plurality of peripheral units selectively addressable by the data processing unit over an address bus with multi bit address codes for the transfer of digital data between the data processing unit and an addressed peripheral unit over a data bus, said data processing unit comprises first means for applying a select signal to a peripheral unit, each peripheral unit includes a storage location for recording a multi-bit identification code which identifies uniquely the peripheral unit, at least one address line of the address bus being connected directly to a respective peripheral unit, whereby said respective peripheral unit being directly selected under application of said select signal to said one address line, characterized in that, said data processing unit comprises second means for applying to the address bus in order to address a peripheral unit a particular address code corresponding to at least a part of said multi-bit identification code for each peripheral unit, and that said select signal being a bit of one value in said part of the identification code.
Claim 2
Dependent Claim
181 words
Digital data apparatus comprising a data processing unit and a plurality of peripheral units selectively addressable by the data processing unit over an address bus with multi bit address codes for the transfer of digital data between the data processing unit and an addressed peripheral unit over a data bus, said data processing unit comprises first means for applying a select signal to a peripheral unit, each peripheral unit includes a storage location for recording a multi-bit identification code which identifies uniquely the peripheral unit, at least one address line of the address bus being connected directly to a respective peripheral unit, whereby said respective peripheral unit being directly selected under application of said select signal to said one address line, characterized in that, said data processing unit comprises second means for applying to the address bus in order to address a peripheral unit a particular address code corresponding to at least a part of said multi-bit identification code for each peripheral unit, and that said select signal being a bit of one value in said part of the identification code.
Claim 3
Dependent Claim
53 words
Digital data apparatus as claimed in Claim 1, characterized in that the data processing unit comprises a flag bit producer for inserting in each identification code at least one flag bit, which value being determined by the number of bits of said one value being contained in said part of the identification code.
Claim 4
Dependent Claim
54 words
Digital data apparatus as claimed in Claim 2, including comparing means in the data processing unit for comparing an address code used to address a peripheral unit with an identification code of a selected peripheral unit, characterized in that said flag bits being compared with test flag bits produced by said flag bit producer.
Claim 5
Dependent Claim
60 words
Digital data apparatus as claimed in any of the preceding Claims in which each peripheral unit comprises at least two sub-units, characterized in that each sub-unit has its own storage location for recording its own identification code, which identification codes for all the sub-units of a peripheral unit have in said part the same one bit of said one value.
Claim 6
Dependent Claim
46 words
Digital data apparatus as claimed in Claim 4, characterized in that other bits in said part which do not serve as select signals in address codes are used singly or in combination to select the sub-units of each peripheral unit in accordance with their respective values.
Claim 7
Dependent Claim
156 words
Digital data apparatus as claimed in any preceding Claim, characterized in that the identification codes in the respective storage locations being recorded by using a writing operation by which writing means in the data processing unit applies all the possible address codes the address bus in turn in a special sequence, and that for each address code the writing means also applies it, with or without flag bits, as data for recording into the storage location of each addressed peripheral unit or sub-unit, the special writing sequence being such that the address code which has all its bits of said one value is written first, followed by the address codes which have all their bits exceptione of said one value, followed by the address codes which have all their bits except two of said one value, and so on, the sequence finishing with the address code which has none of its bits of said one value.
Claim 8
Dependent Claim
31 words
Digital data apparatus as claimed in any preceding Claims, characterized in that said data processing unit is a digitally operable processing unit and said peripheral units are random access memory units.
Claim 9
Dependent Claim
20 words
Digital data apparatus as claimed in Claim 7, characterized in that each memory unit contains the same amount of memory.