EP0071204A2
Expired / Lapsed
EP
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Method for forming recessed dielectric isolation
Assignee: International Business Machines Corp
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Filing: 1982-07-23
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Granted: —
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Expires: 2002-07-23
Abstract
Abstract A method is described for forming the recessed dielectric isolation in a silicon substrate. This method involves first forming trenches (16) which are less than 1 micron in depth in areas of one principal surface of the silicon substrate where isolation is desired. Where, for example, an NPN bipolar transistor structure is planned to be formed it is usually necessary to have a P+ region (6) underneath the recessed dielectric isolation to allow full isolation between the various bipolar transistor devices. A PNP transistor uses an N+ region underneath the isolation. Where a field effect transistor is planned a channel stop (30) can be substituted for the P+ region. Under the circumstance of bipolar devices, the P+ region (6) is formed in the substrate (2) prior to the deposition of an epitaxial layer (8) thereover. The trench formation is caused to be formed through the epitaxial layer and into the P+ regions therein. The surface of the trenches (16) are then oxidized in an oxidizing ambient to form a silicon dioxide layer (18) thereon. A glass (20) is deposited over this principal surface. The glass used has a thermal coefficient of expansion that approximates that of silicon and has a softening temperature of less than 1200°C. The structure is then heated to a temperature that allows the flow of the deposited glass on the surface so as to fill the trenches. The glass on the principal surface above the trench can be removed by a reactive ion etching method. Alternatively and preferably, the glass is removed from areas other than the immediate area of the trench by lithography and etching techniques followed by a second heating of the structure to cause the glass flow to result in surface planarization.
Inventors
- 👤 William Aaron Pliskin
- 👤 Jacob Riseman
- 👤 Joseph Francis Shepard
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 05:47
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/6928; H10P14/6929; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6329; H10P14/6334; H10P14/6342; H10P14/65; H10P14/6502; H10P14/6506; H10P95/00; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0145; H10W10/0148; H10W10/10; H10W10/17
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
108 words
Method for forming recessed dielectric isolation in a silicon substrate comprising: a) forming trenches less than one micron in depth in the areas of one surface of said substrate wherein said isolation is desired; b) oxidizing the surfaces of said trenches to form a silicon dioxide layer thereon; c) depositing a glass having a thermal coefficient of expansion between 20 to 50 x 10 per degree centigrade that approximates that of silicon and having a softening temperature of less than 1200°C onto the said surface of said substrate; and d) heating the structure to cause the flow of said glass on said surface and filling of said trenches.
Claim 2
Dependent Claim
108 words
Method for forming recessed dielectric isolation in a silicon substrate comprising: a) forming trenches less than one micron in depth in the areas of one surface of said substrate wherein said isolation is desired; b) oxidizing the surfaces of said trenches to form a silicon dioxide layer thereon; c) depositing a glass having a thermal coefficient of expansion between 20 to 50 x 10 per degree centigrade that approximates that of silicon and having a softening temperature of less than 1200°C onto the said surface of said substrate; and d) heating the structure to cause the flow of said glass on said surface and filling of said trenches.
Claim 3
Dependent Claim
21 words
Method of claim 1 wherein said trenches are formed by a reactive ion etching process which produces substantially vertical trench walls.
Claim 4
Dependent Claim
28 words
Method of claim 1 wherein a layer of silicon nitride is formed over said silicon dioxide layer in said trenches when said glass has a significant sodium content.
Claim 5
Dependent Claim
37 words
The method of claim 1 wherein said glass is formed by a sedimentation process which involves spray coating, or centrifuging a coating, or a spin-on of a coating of glass particles upon the surfaces of said substrate.
Claim 6
Dependent Claim
13 words
Method of claim 1 wherein said glass is formed by a sputtering process.
Claim 7
Dependent Claim
13 words
Method of claim 1 wherein said glass is formed by an evaporation process.
Claim 8
Dependent Claim
25 words
Method of claim 1 wherein said glass is selected from the group of lead borosilicate glass, calcium alumino borosilicate glass, β-spodumene glass-ceramic, and cordierite glass-ceramic.
Claim 9
Dependent Claim
11 words
Method of claim 1 wherein said glass is substantially sodium free.
Claim 10
Dependent Claim
39 words
Method of claim 1 and further comprising removing glass from said surface by etching in areas other than the immediate areas of said trenches and heating the structure to less than 1000°C to cause glass flow and surface planarization.
Claim 11
Dependent Claim
257 words
Method for forming a bipolar integrated circuit having recessed dielectric isolation in a silicon body comprising: providing a monocrystalline silicon substrate (2); forming doped regions (4) of a first conductivity in said substrate in areas designated to be part of subcollector regions; forming doped regions (6) of a second conductivity in areas designated to form part of a junction isolation which cooperates with said recessed dielectric isolation to isolate regions of said silicon body; growing an epitaxial layer (8) upon said substrate wherein during the growth said doped regions (4) of a first conductivity outdiffuse into said epitaxial layer to fully form the said subcollector regions and, said doped regions of a second conductivity (6) outdiffuse into said epitaxial layer to fully form the said junction isolation regions; forming trenches (16) less than one micron in depth into the areas of said epitaxial layer (8) wherein said isolation is desired and deep enough to penetrate said junction isolation regions (6) thereunder; oxidizing the surfaces of said trenches to form a silicon dioxide layer (18) thereon; depositing a glass (20) having a thermal coefficient of expansion between 20 to 50 x 10 -7 per degree centigrade that approximates that of silicon and having a softening temperature of less than 1200°C onto the said surface of said epitaxial layer; heating the structure to cause the flow of said glass (20) on said surface and filling of said trenches (18); and forming said bipolar transistor devices within the silicon body (25) isolated by said recessed dielectric isolation (6, 18, 20).
Claim 12
Dependent Claim
257 words
Method for forming a bipolar integrated circuit having recessed dielectric isolation in a silicon body comprising: providing a monocrystalline silicon substrate (2); forming doped regions (4) of a first conductivity in said substrate in areas designated to be part of subcollector regions; forming doped regions (6) of a second conductivity in areas designated to form part of a junction isolation which cooperates with said recessed dielectric isolation to isolate regions of said silicon body; growing an epitaxial layer (8) upon said substrate wherein during the growth said doped regions (4) of a first conductivity outdiffuse into said epitaxial layer to fully form the said subcollector regions and, said doped regions of a second conductivity (6) outdiffuse into said epitaxial layer to fully form the said junction isolation regions; forming trenches (16) less than one micron in depth into the areas of said epitaxial layer (8) wherein said isolation is desired and deep enough to penetrate said junction isolation regions (6) thereunder; oxidizing the surfaces of said trenches to form a silicon dioxide layer (18) thereon; depositing a glass (20) having a thermal coefficient of expansion between 20 to 50 x 10 -7 per degree centigrade that approximates that of silicon and having a softening temperature of less than 1200°C onto the said surface of said epitaxial layer; heating the structure to cause the flow of said glass (20) on said surface and filling of said trenches (18); and forming said bipolar transistor devices within the silicon body (25) isolated by said recessed dielectric isolation (6, 18, 20).
Claim 13
Dependent Claim
141 words
Method for forming field effect transistor devices having recessed dielectric isolation in a silicon body comprising: forming trenches (16) less than one micron in depth in the areas of one surface of said body (2) wherein said isolation is desired; forming a channel stop (30) at the bottom of said trenches by ion implantation; oxidizing the surfaces of said trenches to form a silicon dioxide layer (18) thereon; depositing a glass (50) having a thermal coefficient of expansion between 20 to 50 x 10-7 per degree centigrade that approximates that of silicon and having a softening temperature of less than 1200°C onto the said surface of said substrate; heating the structure to cause the flow of said glass (50) on said surface and filling of said trenches (16); and forming said field effect transistor devices within and upon said silicon body.
Claim 14
Dependent Claim
141 words
Method for forming field effect transistor devices having recessed dielectric isolation in a silicon body comprising: forming trenches (16) less than one micron in depth in the areas of one surface of said body (2) wherein said isolation is desired; forming a channel stop (30) at the bottom of said trenches by ion implantation; oxidizing the surfaces of said trenches to form a silicon dioxide layer (18) thereon; depositing a glass (50) having a thermal coefficient of expansion between 20 to 50 x 10-7 per degree centigrade that approximates that of silicon and having a softening temperature of less than 1200°C onto the said surface of said substrate; heating the structure to cause the flow of said glass (50) on said surface and filling of said trenches (16); and forming said field effect transistor devices within and upon said silicon body.
Claim 15
Dependent Claim
20 words
Method of claim 11 wherein said channel stop (30) is P type and said field effect transistors are N type.
Claim 16
Dependent Claim
130 words
Bipolar transistor integrated circuit comprising: a pattern of recessed isolation trenches (16) surrounding regions of monocrystalline silicon; a silicon dioxide layer (18) lining the outer surfaces of said trenches; a glass (20) at least substantially filling the remainder of trenches (16) with the top surface of said trenches being completely covered with said glass; said glass having a thermal coefficient of expansion that approximates that of silicon and having a softening temperature of less than 1200°C; a junction isolation region pattern (6) having the same conductivity type as the base of said bipolar transistors which pattern is located directly below said pattern of recessed isolation trenches (16) and cooperates therewith to isolate said regions (25) of silicon; and bipolar transistors located within at least some of said regions of silicon.
Claim 17
Dependent Claim
130 words
Bipolar transistor integrated circuit comprising: a pattern of recessed isolation trenches (16) surrounding regions of monocrystalline silicon; a silicon dioxide layer (18) lining the outer surfaces of said trenches; a glass (20) at least substantially filling the remainder of trenches (16) with the top surface of said trenches being completely covered with said glass; said glass having a thermal coefficient of expansion that approximates that of silicon and having a softening temperature of less than 1200°C; a junction isolation region pattern (6) having the same conductivity type as the base of said bipolar transistors which pattern is located directly below said pattern of recessed isolation trenches (16) and cooperates therewith to isolate said regions (25) of silicon; and bipolar transistors located within at least some of said regions of silicon.
Claim 18
Dependent Claim
114 words
Field effect transistor integrated-circuit comprising: a pattern of recessed isolation trenches (16) surrounding regions of monocrystalline.silicon; a silicon dioxide layer (18) lining the outer surfaces of said trenches (16); a glass (50) at least substantially filling the remainder of said trenches with the top surface of said trenches being completely covered with said glass; said glass having a thermal coefficient of expansion that approximates that of silicon and having a softening temperature of less than 1200°C; a channel stop pattern (30) located directly below said pattern of recessed isolation trenches (16) and cooperates therewith to isolate said regions of silicon; and field effect transistors located within at least some of said regions of silicon.
Claim 19
Dependent Claim
114 words
Field effect transistor integrated-circuit comprising: a pattern of recessed isolation trenches (16) surrounding regions of monocrystalline.silicon; a silicon dioxide layer (18) lining the outer surfaces of said trenches (16); a glass (50) at least substantially filling the remainder of said trenches with the top surface of said trenches being completely covered with said glass; said glass having a thermal coefficient of expansion that approximates that of silicon and having a softening temperature of less than 1200°C; a channel stop pattern (30) located directly below said pattern of recessed isolation trenches (16) and cooperates therewith to isolate said regions of silicon; and field effect transistors located within at least some of said regions of silicon.
References Cited (Backward Citations)
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