Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
137 words
Method for fabricating self-passivated composite silicon-silicide conductive electrodes on a semiconductor structure including the steps of: providing a conductive first silicon layer on said semiconductor structure, co-depositing over said first silicon layer a silicide-forming metal and silicon and exposing the layered silicon metal structure to a thermally oxidizing atmosphere to grow a predetermined thickness of silicon dioxide on it; characterized in that the co-deposition of silicon and said silicide-forming metal is performed in a substantially stoichiometric ratio to form an alloy. layer having the composition of an intermetallic compound, that on top of the silicon and silicide-forming metal containing layer a second silicon layer is deposited and that the thickness of said second silicon layer provides between 30 and 100 % of the silicon required to grow said predetermined thickness of silicon dioxide during said oxidation step.
Claim 2
Dependent Claim
137 words
Method for fabricating self-passivated composite silicon-silicide conductive electrodes on a semiconductor structure including the steps of: providing a conductive first silicon layer on said semiconductor structure, co-depositing over said first silicon layer a silicide-forming metal and silicon and exposing the layered silicon metal structure to a thermally oxidizing atmosphere to grow a predetermined thickness of silicon dioxide on it; characterized in that the co-deposition of silicon and said silicide-forming metal is performed in a substantially stoichiometric ratio to form an alloy. layer having the composition of an intermetallic compound, that on top of the silicon and silicide-forming metal containing layer a second silicon layer is deposited and that the thickness of said second silicon layer provides between 30 and 100 % of the silicon required to grow said predetermined thickness of silicon dioxide during said oxidation step.
Claim 3
Dependent Claim
17 words
Method according to claim 1, wherein said co-deposited layer has a thickness between 100 and 350 nm.
Claim 4
Dependent Claim
34 words
Method according to claim 1 or 2, wherein the thickness of said first silicon layer is greater than 100 nm, and the thickness of said second silicon layer is between 10 and 100 nm.
Claim 5
Dependent Claim
29 words
Method according to any one of claims 1 to 3, wherein said silicide-forming metal is selected from the group consisting of cobalt, molybdenum, niobium, rhodium, tantalum, titanium and tungsten.
Claim 6
Dependent Claim
34 words
Method according to any one of claims 1 to 4, wherein said structure is heated to a temperature between 600 and 1100 0 C, and preferably to about 1000°C to anneal said alloy layer.
Claim 7
Dependent Claim
43 words
Method according to any one of claims 1 to 5, wherein said second silicon and said co-deposited layers are blanket deposited and further wherein said layers are selectively etched to form patterned electrodes prior to exposing said layered structure to said oxidizing atmosphere.
Claim 8
Dependent Claim
24 words
Method according to any one of claims 1 to 6, wherein said co-deposited layer is formed by co-evaporation of silicon and said silicide-forming metal.
Claim 9
Dependent Claim
34 words
Method according to any one of claims 1 to 7, wherein said co-evaporation is performed after preheating said substrate to between 25 and 350°C, and preferably to about 300°C if the silicide-forming is tungsten.
Claim 10
Dependent Claim
34 words
Method according to any one of claims 1 to 8, wherein the steps of co-depositing said alloy layer and depositing said second silicon layer are sequentially performed within a single deposition chamber without interruption.
Claim 11
Dependent Claim
70 words
Method according to any one of claims 1 to 9 being applied in producing field effect devices, wherein the first polysilicon layer is deposited on a gate dielectric layer provided on a semiconductor substrate, and wherein after forming patterned electrodes from said layers opposite conductivity type regions are formed in said substrate adjacent to at least portions of said patterned electrodes prior to exposing said substrate to said oxidizing atmosphere.