High density imager

Claim 2

A high density charge coupled device imaging array (88) on a single integrated circuit chip, including: a first row (30, 60, 90) of photosites deposited on the chip (28), said photosites being responsive to the incidence of light thereon, a second row (32, 62, 94) of photosites deposited on said integrated circuit chip parallel to said first row of photosites, said second row (94) of photosites being offset from said first row of photosites approximately one-half the length of the individual photosites in said first row such that said second row of photosites are responsive to the incidence of light intermediate the centres of the photosites in said first row of photosites, said first and second rows of photosites comprising a bilinear array.

Claim 3

An array as claimed in claim 1, including: a shield (92) between said first and second rows of photosites to shield each row from the incidence of light on the area defined by the shield.

Claim 4

An array as claimed in claim 2, wherein the area covered by the shield covers an area of said imaging array which could include an equally-sized third row of photosites.

Claim 5

An array as claimed in any preceding claim, including: a first storage register (104) deposited on said integrated circuit chip adjacent to said first row (90) of photosites to receive and store the bits of light information detected by said first row of photosites (90) and converted to electronic charge information, a second storage register (108) deposited on said integrated circuit chip adjacent to said first storage register (104) to receive and store said bits of light information received and stored by said first storage register (104), a third storage register (110) deposited on said integrated circuit chip adjacent to said second storage register (108) to receive and store alternate bits of said light information received and stored by said second storage register (108), a fourth storage register (112) deposited on said integrated circuit chip adjacent to said third storage register (110) to receive and store the remaining bits of said light information received and stored by said second storage register, a fifth storage register (100) deposited on said integrated circuit chip adjacent to said second row (94) of photosites to receive and store alternate intermediate bits of light information detected by said second row (94) of photosites converted to electronic charge information, and a sixth storage register (102) deposited on said integrated circuit adjacent to said fifth storage register (100) to receive and store the remaining intermediate bits of said light information detected by said second row (94) of photosites converted to electronic charge information.

Claim 6

An array as claimed in claim 4, wherein said third, fourth, fifth, and sixth storage registers comprise a quadrilinear array such that all four registers contain the detected light from one line of scan at the same time.

Claim 7

An array as claimed in claim 5, including: transfer gates (96, 98, 104) deposited between the first row (90) of photosites and the first storage register (104), the first storage register (104) and the third (110) and fourth (112) storage registers, the second row (94) of photosites and the fifth (100) and sixth (102) storage registers, said transfer gate means also being deposited on said integrated circuit chip to provide paths for the movement of said electronic charge information.

Claim 8

An array as claimed in any preceding claim, in which the two rows of photosites are separated from each other by a distance equal to the width of one row.

Claim 9

An array as claimed in any of claims 1-3, in which the second row of photosites is contiguous with the first row.

Claim 10

An array as claimed in claim 8, including a storage register (38) deposited on said integrated circuit chip adjacent to said second row (32) of photosites to receive and store the bits of information detected by said row of photosites (32).

Claim 11

An array as claimed in claim 9, including a first shift register (42) deposited on said integrated circuit chip adjacent to said first row (30) of photosites to receive and store the bits of light information detected by said first row of photosites and converted to electronic charge information, and a second shift register (44) deposited on said integrated circuit chip adjacent to said storage register (38) to receive and store said bits of light information received by said storage register (38) from said second row (32) of photosites, said second shift register and said first shift register (42) receiving the bits of light information therefor at the same period.