EP0069762B1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Universal interconnection substrate
Assignee: Energy Conversion Devices Inc
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Filing: 1981-12-22
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Granted: 1989-02-08
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Expires: 2001-12-22
Abstract
Abstract A wafer substrate for integrated circuits (1) which by itself may be made either of conductive or non-conductive material. This substrate carries two planes or layers of patterned metal (19, 20), thus providing two principal levels of interconnection. An insulation layer (21) is placed between the metal layers and also between the lower metal layer and the substrate if the latter is conductive. Connections between the metal layers or between the metal layer and the substrate can be made through via holes in the insulator layer or layers, respectively. The real estate provided by the substrate (1) is divided up into special areas used for inner cells (2) outer cells (3) signal hookup areas (4) and power hookup areas (5). The cells are intended to host the integrated circuit chips (24, 25) and to provide the bonding pads (8) for the signal connections between the chips and the substrate.
Inventors
- 👤 Herbert Stopper
- 👤 Richard A. Flasck
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 23:14
CPC Classifications
H; H05; H05K; H05K1/00; H05K1/02; H05K1/0286; H05K1/0287; H05K1/0289; H10; H10W; H10W72/00; H10W72/50; H10W72/541; H10W72/5449
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
150 words
A substrate for integrated circuitry comprising a base substrate wafer having disposed thereon a first conductive interconnection layer (19) and a second conductive interconnection layer (80) and a layer (21) of insulation separating said first and second interconnection layers, said base substrate being adapted for carrying a plurality of integrated circuit chips thereon, and said first and second interconnection layers being adapted to provide a routing network between said integrated circuit chips by a pattern of interconnection lines for each layer, said first and second interconnection layers being interconnected by through viasthrough said insulating layer at cross-points connecting a line in said first interconnection layer with a line in said second interconnection layer characterised in that at least one of said cross-points is a programmable cross-point wherein said connection is made through an amorphous semiconductor material which can be switched electrically from a high impedance to a low impedance state.
Claim 2
Dependent Claim
150 words
A substrate for integrated circuitry comprising a base substrate wafer having disposed thereon a first conductive interconnection layer (19) and a second conductive interconnection layer (80) and a layer (21) of insulation separating said first and second interconnection layers, said base substrate being adapted for carrying a plurality of integrated circuit chips thereon, and said first and second interconnection layers being adapted to provide a routing network between said integrated circuit chips by a pattern of interconnection lines for each layer, said first and second interconnection layers being interconnected by through viasthrough said insulating layer at cross-points connecting a line in said first interconnection layer with a line in said second interconnection layer characterised in that at least one of said cross-points is a programmable cross-point wherein said connection is made through an amorphous semiconductor material which can be switched electrically from a high impedance to a low impedance state.
Claim 3
Dependent Claim
17 words
A substrate according to claim 1, characterised in that the amorphous semiconductor material is an amorphous chalcogenide.
Claim 4
Dependent Claim
21 words
A substrate according to claim 1, characterised in that integrated circuits are bonded to the substrate to form a hybrid circuit.
Claim 5
Dependent Claim
17 words
A substrate according to claim 1, characterised in that the base substrate is composed of silicon material.
Claim 6
Dependent Claim
39 words
A substrate according to claim 1, characterised in that the substrate is divided into a plurality of areas, respective ones of the areas being adapted to act as inner cells, outer cells, signal hookup areas and power hookup areas.
Claim 7
Dependent Claim
37 words
A substrate according to claim 1, characterised in that areas of the substrate are provided as cells adapted to host integrated circuit chips and to provide bonding pads for signal connections between the chips and the substrate.
Claim 8
Dependent Claim
22 words
A substrate according to claim 6, characterised in that at least one ofthe cells has a plurality of signal pads disposed therein.
Claim 9
Dependent Claim
18 words
A substrate according to claim 7 having disposed thereon an integrated circuit chip in each of the cells.
Claim 10
Dependent Claim
24 words
A substrate according to claim 7, characterised in that the cells are adapted to receive chips covering an area larger that that cell area.
Claim 11
Dependent Claim
24 words
A substrate according to claim 7, characterised in that the cells are adapted to receive chips covering an area smaller that that cell area.
Claim 12
Dependent Claim
26 words
A substrate accordint to claim 7, characterised in that the cells are adapted to receive chips covering an area substantially equal to those of the cells.
Claim 13
Dependent Claim
28 words
A substrate according to claim 7, characterised in that cells are provided on the substrate which are adapted to be universally usable for a combination of chip sizes.
Claim 14
Dependent Claim
46 words
A substrate according to claim 1, characterised in that cells are provided on the substrate adapted to receive chips bonded thereto and having signal bonding pads for signal connection between the chips and the substrate, and power busses are provided along the edges of all cells.
Claim 15
Dependent Claim
21 words
A substrate according to claim 13, characterised in that additional power busses are provided along the centre lines of the cells.
Claim 16
Dependent Claim
23 words
A substrate according to claim 1, characterised in that the lines of the first and second interconnection layers form an orthogonal line pattern.
Claim 17
Dependent Claim
29 words
A substrate according to claim 1, characterised in that the interconnecting lines comprise a plurality of pad lines each having a single pad, and a plurality of net lines.
Claim 18
Dependent Claim
63 words
A substrate according to claim 1, characterised in that the interconnecting lines comprise a set of pad lines, a set of horizontal net lines and a set of vertical net lines disposed perpendicularly to the horizontal net lines, each horizontal net line being connected to a single vertical net line to form a net, and each net being connected to a single pad.
Claim 19
Dependent Claim
16 words
A substrate according to claim 17, characterised in that each pad line crosses each net once.
Claim 20
Dependent Claim
72 words
A substrate according to claim 1, characterised in that the said at least one programmable cross-point is formed by an opening (17) in the layer of insulation between the first and second conductive insulating layers, the opening being filled by a cross-point pad (18) of amorphous semiconductor material which is an insulator and can be switched electrically to be a conductor by the application of a voltage higher than a predetermined voltage.
Claim 21
Dependent Claim
58 words
A substrate according to claim 19, wherein a plurality of conductive lines are formed in one of conductive interconnecting layers, and at least one said conductive lines has a plurality of programmable cross-point pads of amorphous semiconductor material for these cross-points are formed by a single continuous strip running between the said conductive line and the insulating layer.
Claim 22
Dependent Claim
28 words
A substrate according to claim 19, characterised in that the amorphous semiconductor material is applied as a coating between the insulating layer and one of the conductive layers.
Claim 23
Dependent Claim
38 words
A substrate according to claim 1, characterised in that the substrate has a conductive base substrate wafer in contact with a power grid such that power connections may be made directly to a power rail of said grid.
References Cited (Backward Citations)
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