EP0068569A2
Expired / Lapsed
EP
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Digital data apparatus with memory identification
Assignee: Philips Electronics UK Ltd
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Filing: 1982-06-18
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Granted: —
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Expires: 2002-06-18
Abstract
Abstract Digital data apparatus comprising a processing unit which can have access to different numbers of memory units over a common data bus. The processing unit can address selectively the memory units with address codes over an address bus. An address code is valid when there is a corresponding memory unit and invalid when no memory unit is provided in respect of it. The validity of an address code is determined in the processing unit by comparing it with a corresponding identification code read from a memory unit addressed by the code. In order to prevent line capacitance on the data bus simulating identification codes to produce an incorrect comparison, one line of the data bus is given the inverse data bit to that of an expected identification code to overcome any spurious bit due to line capacitance. If the identification code is present, the correct data bit in it prevails over the inverse data bit, resulting in a correct validity comparison. If there is no identification code, because there is no memory unit corresponding to the address code concerned, the inverse data bit remains, resulting in correct invalidity comparison. Fig. 3 shows the relevant circuit elements for the performance of the invention.
Inventors
- 👤 John Ritchie Kinghorn
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 21:18
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0684
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
235 words
Digital data apparatus comprising a data processing unit and a plurality of peripheral units selectively addressable by the data processing unit over an address bus with bi-level address codes for the transfer of digital data between the data processing unit and an addressed peripheral unit over a data bus, each peripheral unit having a special storage location for the storage of a multi-bit identification code which identifies uniquely the peripheral unit, characterised in that the data processing unit includes interrogation means for testing the presence of a peripheral unit corresponding to an address code applied to the address bus, said interrogation means comprising first means for requesting from that addressed peripheral unit during an interrogation period the transfer of its identification code to the data processing unit over the data bus for comparison with a corresponding code in the data processing unit, second means for causing at least one data line of the data bus to assume during said interrogation period an inverse active level which is opposite to the proper active level on that data line in response to a correct application of the relevant bit of the identification code on that data line, said inverse active level being de-activated by said second means in the presence of the proper active level on the data line, and third means for sensing as part of said comparison the prevailing active level of the data line.
Claim 2
Dependent Claim
235 words
Digital data apparatus comprising a data processing unit and a plurality of peripheral units selectively addressable by the data processing unit over an address bus with bi-level address codes for the transfer of digital data between the data processing unit and an addressed peripheral unit over a data bus, each peripheral unit having a special storage location for the storage of a multi-bit identification code which identifies uniquely the peripheral unit, characterised in that the data processing unit includes interrogation means for testing the presence of a peripheral unit corresponding to an address code applied to the address bus, said interrogation means comprising first means for requesting from that addressed peripheral unit during an interrogation period the transfer of its identification code to the data processing unit over the data bus for comparison with a corresponding code in the data processing unit, second means for causing at least one data line of the data bus to assume during said interrogation period an inverse active level which is opposite to the proper active level on that data line in response to a correct application of the relevant bit of the identification code on that data line, said inverse active level being de-activated by said second means in the presence of the proper active level on the data line, and third means for sensing as part of said comparison the prevailing active level of the data line.
Claim 3
Dependent Claim
30 words
Digital data apparatus as claimed in Claim 1, characterised in that the identification code allocated to each peripheral unit is the same as the address code for the peripheral unit.
Claim 4
Dependent Claim
42 words
Digital data apparatus as claimed in Claim 2, characterised in that an addresser circuit in the data processing unit is operable to effect a counting sequence to produce successive addresses which are recorded in the storage locations of the respective peripheral units.
Claim 5
Dependent Claim
36 words
Digital data apparatus as claimed in Claim ? or Claim 3, characterised in that the data bus is used additionally for addressing the storage location of a peripheral unit which is addressed over the address bus.
Claim 6
Dependent Claim
44 words
Digital data apparatus as claimed in Claim 4, characterised in that the data bus is further used on a multiplex basis as a combined data/address bus for addressing other storage or other elements of a peripheral unit which is addressed over the address bus.
Claim 7
Dependent Claim
25 words
Digital data apparatus as claimed in Claim 3, characterised in that said address bus is combined with the combined data/address bus on a multiplex basis.
Claim 8
Dependent Claim
139 words
Digital data apparatus as claimed in any one of Claims 2 to 6, characterised in that said interrogation period is divided into a first part in which said first means is operable, and second and third parts in which said second means is operable, said second means comprising a low impedance current driver circuit which is operable to pre-charge the data line to the inverse active level in the second part and a high impedance current driver circuit which is operable to tend to maintain the pre-charged state of the data line in the third part, and each peripheral unit includes a low impedance current driver circuit which is operable when the unit is addressed to charge the data line to the proper active level in the third part, notwithstanding the operation of the high impedance current driver circuit.
Claim 9
Dependent Claim
53 words
Digital data apparatus as claimed in Claim 7, characterised in that the low impedance current driver circuit in the data processing unit and the low impedance current driver circuit in each peripheral unit are otherwise normally used for data transfer between the data processing unit and the peripheral unit over the data bus.
Claim 10
Dependent Claim
30 words
Digital data apparatus as claimed in any preceding Claim, characterised in that said main unit is a digitally operable processing unit and said peripheral units are random access memory units.
Claim 11
Dependent Claim
20 words
Digital data apparatus as claimed in Claim 9, characterized in that each memory unit contains the same amount of memory.
References Cited (Backward Citations)
No citation records indexed.
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