EP0068143A2
Expired / Lapsed
EP
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Analog to digital converter
Assignee: International Business Machines Corp
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Filing: 1982-05-24
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Granted: —
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Expires: 2002-05-24
Abstract
Abstract A pipelined charge coupled analog to digital converter which provides a plurality of serially arranged pipelined stages that are connected to pass signal and reference charge packets from stage to stage in a serial progression. The converter includes one stage for each bit desired in the output bit stream so that a converter having n stages provides an n bit digital word corresponding to the input analog signal charge. While the time necessary to perform the analog to digital conversion is the sum of operating times of all the stages, because the converter is pipelined, each successive n bit digital word representing a different successive charge packet is produced succeeding a preceding digital word representing a preceding signal charge packet, by a delay equal to the processing time of only a single stage. The Figure shows a three stage converter. In the initial stage, the reference charge packet (Q r ) from generator (CG) is halved by splitter (51) and the halved charged held by (FET FG1). The input charge is held on (FET FG2) and the two charges compared at (C1). The result of the comparison is delayed via delay stages (DR) and also used to control switches (SW1, SW2). In the intermediate or typical stage, the comparator (C 2 ) similarly compares charges held on (FET FG3 and FG4). the magnitude of the charges to be compared is determined by the setting of the switches (SW1, SW2). The final stage similar to a typical stage but includes charge drums D. The stages implements the algorithm where b n , is 0 or 1 depending on the comparison ( ) and b x is the inverse of bx.
Inventors
- 👤 Eugene Stewart Schlig
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 13:40
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
77 words
A charge coupled analog to digital system including a plurality of pipelined stages for performing successive approximations on a reference analog charge Q r and an input signal charge Q s , characterised in that said pipelined stages include charge processing means each coupled only to directly adjacent stages for performing an inequality function to provide a bit string b 1 through b N representing a digital representation of said input analog signal charge Q s .
Claim 2
Dependent Claim
77 words
A charge coupled analog to digital system including a plurality of pipelined stages for performing successive approximations on a reference analog charge Q r and an input signal charge Q s , characterised in that said pipelined stages include charge processing means each coupled only to directly adjacent stages for performing an inequality function to provide a bit string b 1 through b N representing a digital representation of said input analog signal charge Q s .
Claim 3
Dependent Claim
24 words
A system as claimed in claim 1, in which said charge processing means includes comparator means for performing an inequality function on simultaneous inputs.
Claim 4
Dependent Claim
25 words
A system as claimed in claim 1, in which said charge processing means includes comparator means for performing an inequality function on sequentially presented inputs.
Claim 5
Dependent Claim
172 words
A system as claimed in claim 2 or 3 which includes a different stage for each bit, b 1 through b N of said digital represention, further characterised in that each stage, other than an initial and final stage comprise: charge splitter means subjected to an input charge packet Qi for delivering, on separate charge transfer paths, a pair of charge packets Qi/2; a pair of commonly controlled charge switching means, each with a charge input and a pair of outputs, each said charge switching means connected to receive a one of said charge packets Qi/2; a single electrode and means coupling an output of each of said charge switching means to said electrode; and a pair of field gate means for generating input voltages for said comparator means each coupled to other outputs of said charge switching means; and means for controlling said charge switching means whereby a charge packet Qi/2 is input to one or another of said field gate means regardless of a condition of said charge switching means.
Claim 6
Dependent Claim
31 words
A system as claimed in claim 4, further characterised in that said means for controlling said charge switching means includes an output from a comparator means of a directly preceding stage.
Claim 7
Dependent Claim
26 words
A system as claimed in claim 4 or 5, which futher includes a deskewing register with at least one stage in each of said pipelined stages.
Claim 8
Dependent Claim
263 words
A system as claimed in claim 2 or 3 which includes a plurality of stages, a different stage for each of said bits b 1 through b in said digital representation, further characterised in that each of said stages, other than an initial and final stage comprising: charge splitter means responsive to an input charge packet Q i for providing, on two separate paths, an output charge packet Q i /2; charge switching means with an input responsive to one of said charge packets Q i/ 2 and a pair of outputs; a charge storage site with two inputs for temporarily retaining an input charge packet and summing a second charge packet therewith; field gate means with two inputs for summing two input charge packets, if presented, and for converting a resulting charge packet to an output voltage and for passing said resulting charge packet to a subsequent stage, first means connecting said switching means outputs to said charge storage site and to said field gate means, second means connecting said charge storage site to said field gate means, third means connecting an output of said filed gate means to a subsequent stage, fourth means connecting the other output of said charge splitting means connecting the other output of said charge splitting means to said subsequent stage; said comparator means responsive to sequential inputs from said field gate means to perform an inequality function, means conducting an output of said comparator means as one of said bits b 1 through b N and for controlling the charge switching means of said subsequent stages.
Claim 9
Dependent Claim
140 words
A charge coupled processing system including a plurality of generally parallel charge packet conducting paths, charge merging site means for merging charge packets and for generating an output charge packet 0 0 representing said merged charge packets; charge splitting means responsive to an input charge pack Q i for generating on two separate conducting paths, a charge packet Q i /2; a pair of commonly controlled charge switching means each responsive to one of said charge packets Q i /2, and each with a pair of outputs; a first output of one of said switching means and second output of another of said switching means providing inputs to said charge merging site; whereby, regardless of the condition of said charge switching means, a charge packet Q i/ 2 is available for insertion to one of said parallel charge conducting paths.
Claim 10
Dependent Claim
140 words
A charge coupled processing system including a plurality of generally parallel charge packet conducting paths, charge merging site means for merging charge packets and for generating an output charge packet 0 0 representing said merged charge packets; charge splitting means responsive to an input charge pack Q i for generating on two separate conducting paths, a charge packet Q i /2; a pair of commonly controlled charge switching means each responsive to one of said charge packets Q i /2, and each with a pair of outputs; a first output of one of said switching means and second output of another of said switching means providing inputs to said charge merging site; whereby, regardless of the condition of said charge switching means, a charge packet Q i/ 2 is available for insertion to one of said parallel charge conducting paths.
Claim 11
Dependent Claim
32 words
A system as claimed in claim 8 which includes second charge splitting means responsive to said charge packet Q for producing on two separate charge conducting paths, a charge packet_Q o /2.
Claim 12
Dependent Claim
78 words
A system as claimed in claim 11 which includes a second pair of commonly controlled charge switching means each with an input responsive to one of said charge packets Q/2, and each with a pair of outputs, and second charge merging site means coupled to one of each of said pair of outputs whereby, regardless of the condition of said second charge switching means a charge packet Q /2 is available at said second charge merging site means.
Claim 13
Dependent Claim
106 words
A system as claimed in claim 10, further comprising a typical stage of a pipelined A/D converter in which one said charge conducting path is a reference packet path and another said charge conducting path is a signal packet path, said typical stage including said charge merging site means, said commonly controlled charge switching means and said charge splitting means, and further comprising a pair of field gates, each in one of said charge conducting paths and a voltage comparator with two inputs, one coupled to each of said field gates and an output for controlling a commonly controlled charge switching means of a subsequent stage.
References Cited (Backward Citations)
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