EP0067667A2
Expired / Lapsed
EP
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Data processing system
Assignee: EMC Corp
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Filing: 1982-06-10
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Granted: —
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Expires: 2002-06-10
Abstract
Abstract The system employs a fixed point arithmetic unit (ALU) - and a separate floating point arithmetic unit (FPU) controlled by a common microinstruction store. Most fields of the 80-bit microinstructions control both the ALU and the FPU, including a source field ALUS an operation field ALUOP. A further 2-bit field EXT determines whether the FPU performs double or single precision arithmetic, in which the operation defined by ALUOP is carried out respectively by all of 16 4-bit slice units and by the top 6 slice units only for 56 and 24 bit results, with 8 guard bits in either case. As well as a destination field ALUD for the ALU there is a separate destination field FPUD for the FPU and each such field is set to disable the output of its respective unit when the output is required from the other unit. Carry-in bits for bits 55 and 23 are entered at bit 63 and propagated through the lower bit slice units to avoid multiplexing in to the higher bit slice units.
Inventors
- 👤 Robert William Beauchamp
- 👤 Jonathan Seth Blau
- 👤 James B. Stein
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 05:00
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/226; G06F9/30; G06F9/30003; G06F9/30007; G06F9/3001; G06F9/30014; G06F9/30181; G06F9/38; G06F9/3885
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
94 words
A data processing system handling both fixed point and floating point computation operations, comprising an arithmetic unit for profiding fixed point arithmetic computations, a floating point unit for providing floating point arithmetic computations and a single control store means for supplying microinstructions to control the operations of both the units, characterised in that both of the units are responsive to a plurality of commonly shared control fields of the microinstructions during their respective operations and in that the floating point unit is further responsive to at least one additional control field during its operation.
Claim 2
Dependent Claim
94 words
A data processing system handling both fixed point and floating point computation operations, comprising an arithmetic unit for profiding fixed point arithmetic computations, a floating point unit for providing floating point arithmetic computations and a single control store means for supplying microinstructions to control the operations of both the units, characterised in that both of the units are responsive to a plurality of commonly shared control fields of the microinstructions during their respective operations and in that the floating point unit is further responsive to at least one additional control field during its operation.
Claim 3
Dependent Claim
56 words
A system in accordance with claim 1, characterised in that the arithmetic computation unit is responsive to a selected value of a first control field for preventing the use of any fixed point computation results from the arithmetic unit when the floating point unit is supplying its floating point computation result to the data processing system.
Claim 4
Dependent Claim
58 words
A system in accordance with claim 1 or 2, characterised in that the floating point unit is responsive to a selected value of a second control field for preventing the use of any floating point computation results from the floating point unit when the arithmetic unit is supplying its fixed point computation result to the data processing system.
Claim 5
Dependent Claim
44 words
A system in accordance with claim 3, the first and second control fields are fields which identify respectively the destination of a fixed point computation result from the arithmetic unit and the destination of a floating point computation result from the floating point unit.
Claim 6
Dependent Claim
69 words
A system in accordance with claim 4, characterised in that the selected value of the arithmetic destination control field is set for a no-load operation when the floating point unit is supplying its result to the data processing system and the selected value of the floating point destination control field is set for a no-load operation when the arithmetic unit is supplying its result to the data processing system.
Claim 7
Independent Claim
62 words
A system in accordance with any of claims 1 to 5, characterised in that a common control field of the control store is used to identify the source of data which is to be supplied either to the arithmetic unit when it is computing a fixed point result or to the floating point unit when it is computing a floating point result.
Claim 8
Dependent Claim
56 words
A system in accordance with claim 6, characterised in that a common control field of the control store is used to identify the operation which is to be performed by either the arithmetic unit when it is performing a fixed point operation or the floating point unit when it is performing a floating point operation. '
Claim 9
Independent Claim
47 words
A system according to any of claims 1 to 7, characterised in that the said at least one additional control field comprises a control field for identifying whether the floating point unit is operating on data words of a first or a second number of data bits.
Claim 10
Dependent Claim
41 words
A system in accordance with claim 8, characterised in that the first number is 32 bits for providing a 24 bit floating point mantissa result and the second number is 64 bits for providing a 56 bit floating point mantissa result.
Claim 11
Dependent Claim
71 words
A system in accordance with claim 9, characterised in that, when the control field identifies a 32 bit operation, the field controls the operation of the floating point unit in a manner such that the operands of the computation used for the first 24 bits of the floating point words are controlled by a microinstruction from the control store and the remaining 40 bits of the floating point words are zero.
Claim 12
Dependent Claim
126 words
ll. A data processing system having a floating point unit for providing floating point computation operations, the floating point unit including processing means for providing an overall computation result comprising a first plurality of bits representing a desired floating point computation result and a second plurality of bits not used in this desired computation result; and means for providing a carry-in bit to be added to the floating point computation result; characterised by means for adding the carry-in bit to the least significant bit of the overall computation result and for causing the carry-in bit to be effectively propagated through the processing means so as to be added to the least significant bit of the first plurality of bits to form the floating point computation result.
Claim 13
Dependent Claim
126 words
ll. A data processing system having a floating point unit for providing floating point computation operations, the floating point unit including processing means for providing an overall computation result comprising a first plurality of bits representing a desired floating point computation result and a second plurality of bits not used in this desired computation result; and means for providing a carry-in bit to be added to the floating point computation result; characterised by means for adding the carry-in bit to the least significant bit of the overall computation result and for causing the carry-in bit to be effectively propagated through the processing means so as to be added to the least significant bit of the first plurality of bits to form the floating point computation result.
Claim 14
Dependent Claim
130 words
A system in accordance with claim 11, characterised in that the processor means comprises a plurality of multiple-bit slice processor units each processing selected bit slices of floating point operands to provide the overall computation result, the overall result being formed of a plurality of bit slices each effectively provided with a carry-in bit from an adjacent lower significant bit slice processor unit and effectively supplying a carry-out bit to an adjacent higher significant bit slice processor unit, the carry-in bit added to the least significant bit of the overall result being effectively propagated through the plurality of bit slice processors which form the second plurality of bits so as to be added to the bit slice which forms the least significant bit slice of the first plurality of bits.
Claim 15
Dependent Claim
67 words
A system in accordance with claim 12, characterised in that the processing means has an operating characteristic such that when a bit slice processor unit thereof is placed in an AND operating condition and at least one of the operands of the bit slice processor unit is set to zero, the carry-in bit is effectively propagated through the bit slice processor unit as the carry-out bit thereof.
Claim 16
Dependent Claim
99 words
A system in accordance with claim 13, characterised in that each bit slice processor unit is capable of asserting a propagate bit or a generate bit and the means for adding the carry-in bit and for causing the carry-in bit to be effectively propagated through the bit slice processor unit includes a plurality of look-ahead logic means responsive to the bit slice processor units whereby, when a bit slice processor unit asserts its propagate bit but does not assert its generate bit, the look-ahead logic means associated therewith propagates its carry-in bit but does not generate a carry-out bit.
Claim 17
Dependent Claim
88 words
A system in accordance with claim 13 or 14, characterised in that each of the bit slice processor units which form the second plurality of bits is placed in an AND operating condition and at least one of the floating point operands in the bit slice processor units is set to zero, whereby the carry-in bit is effectively propagated through each said bit slice thereof, the carry-in bit being added to the least significant bit of the first plurality of bits to form the floating point computation result.
Claim 18
Independent Claim
28 words
A system in accordance with any of claims 12 to 15, characterised in that the bit slice processor units each process 4 bits of the floating point operands.
Claim 19
Independent Claim
23 words
A system in accordance with any of claims 12 to 16, characterised in that the overall floating point computation result comprises 64 bits.
Claim 20
Dependent Claim
27 words
A system in accordance with claim 17, characterised in that the first plurality of bits comprises 24 bits and the second plurality of bits comprises 40 bits.
Claim 21
Dependent Claim
27 words
A system in accordance with claim 17, characterised in that the first plurality of bits comprises 56 bits and the second plurality of bits comprises 8 bits.
Claim 22
Dependent Claim
75 words
2 0 . A system in accordance with any of claims 11 to 19, characterised in that the floating point computation result is an unrounded result and the means providing the carry-in bit comprises means for providing a round bit as the carry-in bit which is added to the least significant bit of the overall computation result, the round bit thereby being added to the unrounded result to produce a rounded floating point computation result.
Claim 23
Independent Claim
69 words
A system in accordance with any of claims 11 to 19, characterised in that the means providing the carry-in bit comprises means responsive to a carry-in bit supplied from a source external to the floating point computation unit as the carry-in bit which is added to the least significant bit of the overall computation result, the externally supplied carry-in bit thereby being added to the floating point computation result.
References Cited (Backward Citations)
No citation records indexed.
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