EP0067384A2 — Circuit for serializing and deserializing digital…

Claim 1

Independent Claim 129 words

1 . A circuit for serializing and deserializing digital data transferred between parallel and serial devices of a digital data processing system comprising: A. first shift register means including serial input and output ports and parallel input and output ports, B. second shift register means including serial input and output ports and parallel input and output ports, and C. control means for alternately selecting`añd enabling each of said first and second shift register means so that, in the serial-to-parallel mode of operation, one shift register means serially receives data bits while the other shift register means transmits a parallel word, and in the parallel-to-serial mode of operation, one shift register means receives a parallel word while the other shift register means transmits a parallel word as serial data bits.

Claim 2

Dependent Claim 129 words

1 . A circuit for serializing and deserializing digital data transferred between parallel and serial devices of a digital data processing system comprising: A. first shift register means including serial input and output ports and parallel input and output ports, B. second shift register means including serial input and output ports and parallel input and output ports, and C. control means for alternately selecting`añd enabling each of said first and second shift register means so that, in the serial-to-parallel mode of operation, one shift register means serially receives data bits while the other shift register means transmits a parallel word, and in the parallel-to-serial mode of operation, one shift register means receives a parallel word while the other shift register means transmits a parallel word as serial data bits.

Claim 3

Dependent Claim 165 words

A circuit as recited in claim 2 for serializing and deserializing digital data wherein said control means further includes: i. means responsive to first control signal (POM) for enabling said circuit to operate in a serial-to-parallel mode or parallel-to-serial mode, ii. means for generating a second control signal (PRDY) when said first control signal (POM) indicates a serial-to-parallel mode of operation for indicating that a selectable one of said shift register means is ready to transfer a parallel word, and means responsive to a third control signal (DR) that indicates that a parallel word transmitted by said selected shift register means has been received, and iii. means for generating a fourth control signal (PRDY) when said first control signal (POM) indicates a parallel-to-serial operation for indicating that a selectable one of said shift register means is ready to receive a parallel word, and means responsive to a fifth control signal (PLS) for effecting a transfer of a parallel word to said selected shift register means.

Claim 4

Dependent Claim 124 words

A circuit as recited in claims 1 or 2 for serializing and deserializing digital data further including: D. automatic starting and synchronizing means (18) connected to said first shift register means and being responsive to a predetermined N-bit sequence of serial data bits characterized by having auto-correlation properties such that the number of true comparisons between respective bits of said N-bit sequence and the data bits thereof that are present in the first shift register means during shifting is relatively small until all N bits of said N-bit sequence are shifted into said first shift register means thereby to generate a sixth control signal (ACD) that automatically starts and synchronizes parallel word transfer operations when the circuit operates in the serial-to-parallel mode of operation.

Claim 5

Dependent Claim 61 words

A circuit as recited in claim 3 for serializing and deserializing digital data wherein said automatic starting and synchronizing means detects a predetermined sequence of serial data bits that possess auto-correlation properties such that, during shifting, no more than K being less than N/ 2 will be in agreement until all N bits are present in said first shift register means.

Claim 6

Dependent Claim 64 words

A circuit as recited in claim 4 for serializing and deserializing digital data wherein said sixth control signal (ACD) is enabled by threshold means when L bits being less than N bits but greater than K bits are in agreement thereby to enable the circuit to start parallel word transfer operation when up to N-L bits of the predetermined N-bit sequence are in error.

Claim 7

Dependent Claim 41 words

A circuit as recited in claim 5 for serializing and deserializing digital da. 3 wherein N equals twelve, K equals five, L equals nine, and said predetermined N-bit sequence equals the sequence 100110101111 being preceded by a preamble comprised of zeroes.

Claim 8

Dependent Claim 38 words

7 . A circuit as recited in claim 2 for serializing and deserializing digital data further including variable bit-length control means responsive to a variable bit-length control signal (WLSO,WLS1) for effecting transfers of parallel words of selectable bit-lengths.

Claim 9

Dependent Claim 39 words

A circuit as recited in claim 7 for serializing and deserializing digital data wherein said variable bit-length control means selectively enables said first and second register means to transmit and receive parallel 8-bit words, 10-bit words, or 16-bit words.

Claim 10

Dependent Claim 105 words

A circuit for serializing and deserializing digital data transferred between parallel and serial devices of a digital data processing system comprising: A. plural shift register means, each including serial input and output ports and parallel input and output ports, B. control means for periodically selecting and enabling each of said shift register means so that, in the serial-to-parallel mode of operation, one shift register means serially receives data bits while another shift register means transmits a parallel word, and in the parallel-to-serial mode of operation, one shift register means receives a parallel word while another shift-register means transmits a parallel word as serial data bits.

Claim 11

Dependent Claim 105 words

A circuit for serializing and deserializing digital data transferred between parallel and serial devices of a digital data processing system comprising: A. plural shift register means, each including serial input and output ports and parallel input and output ports, B. control means for periodically selecting and enabling each of said shift register means so that, in the serial-to-parallel mode of operation, one shift register means serially receives data bits while another shift register means transmits a parallel word, and in the parallel-to-serial mode of operation, one shift register means receives a parallel word while another shift-register means transmits a parallel word as serial data bits.

Claim 12

Dependent Claim 165 words

A circuit as recited in claim 9 for serializing and deserializing digital data wherein said control means further includes: i. means responsive to first control signal (POM) for enabling said circuit to operate in a serial-to-parallel mode or parallel-to-serial mode, ii. means for generating a second control signal (PRDY) when said first control signal (POM) indicates a serial-to-parallel mode of operation for indicating that a selectable one of said shift register means is ready to transfer a parallel word, and means responsive to a third control signal (DR) that indicates that a parallel word transmitted by said selected shift register means has been received, and iii. means for generating a fourth control signal (PRDY) when said first control signal (POM) indicates a parallel-to-serial operation for indicating that a selectable one of said shift register means is ready to receive a parallel word, and means responsive to a fifth control signal (PLS) for -effecting a transfer of a parallel word to said selected shift register means.

Claim 13

Dependent Claim 179 words

A circuit for detecting the transmission of a predetermined N-bit sequence of data bits preceded by a predetermined preamble of data bits when some of the bits of said N-bit sequence are erroneous, said predetermined N-bit sequence being characterized by having desirable auto-correlation properties such that the number of true comparisons between respective bit positions thereof when shifted is relatively small until all N bits thereof are compared, said circuit comprising: A. receiving means for serially receiving said transmitted sequence of data bits, B. code means for producing N code signals that correspond in an ordered sequence to the N data bits of said predetermined N-bit sequence, ordered sequence of said N code signals being the bit pattern having substantially the highest minimum distance for a pattern of length N, C. comparing means for respectively comparing, upon receipt of each serially transmitted data bit, all received data bits with said N code signals, and D. threshold means for generating a detect signal that indicates the transmission of said N-bit sequence even though some of the bits thereof are erroneous.

Claim 14

Dependent Claim 179 words

A circuit for detecting the transmission of a predetermined N-bit sequence of data bits preceded by a predetermined preamble of data bits when some of the bits of said N-bit sequence are erroneous, said predetermined N-bit sequence being characterized by having desirable auto-correlation properties such that the number of true comparisons between respective bit positions thereof when shifted is relatively small until all N bits thereof are compared, said circuit comprising: A. receiving means for serially receiving said transmitted sequence of data bits, B. code means for producing N code signals that correspond in an ordered sequence to the N data bits of said predetermined N-bit sequence, ordered sequence of said N code signals being the bit pattern having substantially the highest minimum distance for a pattern of length N, C. comparing means for respectively comparing, upon receipt of each serially transmitted data bit, all received data bits with said N code signals, and D. threshold means for generating a detect signal that indicates the transmission of said N-bit sequence even though some of the bits thereof are erroneous.

Claim 15

Dependent Claim 42 words

1 2. A circuit as recited in claim 11 wherein said N-bit sequence is further characterized in that, during shifting, no more than K being less than N/2 will be in agreement until all N bits are present in said receiving means.

Claim 16

Dependent Claim 32 words

A circuit as recited in claim 12 wherein said threshold means generates said detect signal when L or more bits are in agreement, L being less than N, but greater than K.

Claim 17

Dependent Claim 35 words

A circuit as recited in claim 13 wherein N equals twelve, K equals five, L equals nine, and said predetermined N-bit sequence of data bits equals 100110101111 being preceded by a preamble comprised of zeroes.

Circuit for serializing and deserializing digital data

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