I/O controller with a dynamically adjustable cache memory

Claim 2

Controller I/O for transferring data between a processor and a plurality of peripheral data storage units for storing blocks of data, each block including n data records and a unique file system address; said controller being characterized in that it comprises : a high speed cache memory for storing a portion of the data stored in said peripheral data storage units to speed up the transfer of data between said host processor and said units; a microprocessor for controlling the movement of the data blocks into and out of said cache memory, control means for allocating different storage areas in said cache memory to the different ones of said peripheral data storage units, for determining the relative frequencies at which each of said units are accessed, and for adjusting the amount of said cache memory allocated to each of said units so that this amount, above a predetermined minimum, is proportional to its relative access frequency.

Claim 3

The controller according to claim 1 in which : each data block is assigned a hash entry number, said cache memory storing a first plurality of data blocks having the same corresponding hash entry number and different file system addresses and a second plurality of data blocks all having hash entry numbers different from one another; and said control means comprise directory table means for listing the blocks currently stored in said cache memory, said directory table means having a plurality of directory table positions each identified by a unique hash entry number and each having at least a file system address portion for indicating the file system address of the data blocks listed at said position, each of said second plurality of data blocks being listed at their home positions in said directory table means, i.e., at the positions identified by their hash entry numbers, whereby the listing of each of said second plurality of data blocks comprises a home entry, one of said first plurality of data blocks being listed at a home position identified by said same corresponding hash entry number and comprising a home entry and the remainder of said first plurality of data blocks being listed at directory table positions which are not home positions for any data block currently stored in said cache memory and thereby comprising conflict entries, whereby a requested data block is not currently stored in said cache memory if there is no home entry at the home position of said requested data block in said directory table.

Claim 4

The controller according to claim 2, wherein each directory table position includes forward pointer and backward pointer portions pointing to other positions of said directory table, and each of the directory table positions corresponding to said first plurality of data blocks are linked together in a conflict chain via their forward and backward pointers, with said conflict chain beginning at the home position of said one of said first plurality of data blocks, whereby a requested data block is not currently stored in said cache memory if there is currently a home entry at the home position of said requested data block but if said requested data block is not included in a conflict chain beginning at said home position.

Claim 5

The controller according to claim 3, wherein all unused directory table positions are linked together in a free chain via said forward and backward pointers with one of said unused directory table positions being designated as a first free entry.

Claim 6

The controller according to claim 3 or 4 wherein each directory table position includes at least a further portion for indicating if said position is currently occupied by a home entry or if said position is currently occupied by a conflict entry.

Claim 7

The controller according to any one of claims 2 to 5 further comprising priority table means for listing said directory table entries in a priority order.

Claim 8

The controller according to claim 6, wherein said priority table means comprises a Least Recently Used (LRU) table for listing the blocks of data stored in said cache memory in order of their most recent use, with the most recently requested data block in said cache memory being assigned the highest priority and the least recently used data block in said cache memory being assigned a lowest priority.

Claim 9

The controller according to any one of claims 1 to 7, wherein each block of data stored in said peripheral data storage units comprises a sequence of n data records consecutively designated R 1 -R n including requested data record R m , where n and m are positive integers and m≤n, said controller transferring to said cache memory only a first block of data including said requested data record if m<T1, where T 1 is a positive integer, with 1≦T 1 <n and transfers both said first block of data and a second block of data to said cache memory if m≧T 1 .

Claim 10

The controller according to claim 8, wherein said controller transfers only said first data block to said cache memory if said second data block is already in said cache memory.

Claim 11

The controller according to claim 8 or 9, wherein when said host processor requests a plurality of data records located in said memory unit in different first data blocks, the first data blocks including requested records which are not already stored in said cache memory being first transferred and said second data block being transferred to said cache memory only in accordance with the position of the last requested data record in its data block and only if the data block containing the last requested record is not presently stored in said cache memory.

Claim 12

The controller according to any one of claims 8, 9 or 10, wherein a third block of data is transferred to said cache memory if m>T 2 where T 2 is a positive integer with T 1 <T 2 <n.

Claim 13

The controller according to any one of the preceding claims, further comprising : means for determining the number of consecutive data blocks requested at one time by said processor and for preventing the transfer of data from said a peripheral data storage unit to said cache memory if said number of consecutive data blocks exceeds a predetermined value.