EP0066376A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Data processing system
Assignee: Hitachi Ltd
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Filing: 1982-05-06
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Granted: —
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Expires: 2002-05-06
Abstract
Abstract In a data processing system having an instruction buffer (23), inconsistency between a memory (MS4) and the instruction buffer occurs by a store operation to the memory if an instruction in the store area has been prefetched to the instruction buffer. The changing on the memory of the content prefetched to the instruction buffer, and the proceeding of the execution of the instruction to the changed instruction are detected based on an instruction fetch address of an instruction to be fetched from the memory to the instruction buffer, an execution instruction address of an instruction to be executed, information on a byte position at which the instruction to be executed is stored, a store address by a store instruction and information on a byte position which is changed by a store operation when the execution of the instruction proceeds to the changed instruction, the content of the instruction buffer is invalidated.
Inventors
- 👤 Kanji Kubo
- 👤 Tsugio Momose
- 👤 Chikahiko Izumi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 07:22
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3812
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
244 words
A data processing system in which instructions are prefetched from a main storage (MS4) to an instruction buffer (23) in advance of the execution of an instruction and the instructions are read out from said instruction buffer for execution, comprising: means (33) for specifying an instruction fetch address of an instruction to be fetched from said main storage to said instruction buffer; means (41, 51) for specifying an execution instruction address of an instruction to be executed and first information indicating a byte position at which said instruction is stored; means (2, 50) for specifying a store address by a store instruction and second information indicating a byte position which is changed by a store operation; detection means (55, 60, 64) for detecting that the content prefetched to said instruction buffer has changed on said main storage and that the execution of the instruction has proceeded to the changed instruction, based on said fetch address, said execution instruction address, said first information, said store address and said second information; suppression means (71, 226) for suppressing the prefetch of the instruction from said main storage to said instruction buffer in response to the detection by said detection means that the content prefetched to-said instruction buffer has changed on said main storage; and invalidating means (79, 222) for invalidating the content of said instruction buffer in response to the detection by said detection means that the execution of the instruction has proceeded to the changed instruction.
Claim 2
Dependent Claim
244 words
A data processing system in which instructions are prefetched from a main storage (MS4) to an instruction buffer (23) in advance of the execution of an instruction and the instructions are read out from said instruction buffer for execution, comprising: means (33) for specifying an instruction fetch address of an instruction to be fetched from said main storage to said instruction buffer; means (41, 51) for specifying an execution instruction address of an instruction to be executed and first information indicating a byte position at which said instruction is stored; means (2, 50) for specifying a store address by a store instruction and second information indicating a byte position which is changed by a store operation; detection means (55, 60, 64) for detecting that the content prefetched to said instruction buffer has changed on said main storage and that the execution of the instruction has proceeded to the changed instruction, based on said fetch address, said execution instruction address, said first information, said store address and said second information; suppression means (71, 226) for suppressing the prefetch of the instruction from said main storage to said instruction buffer in response to the detection by said detection means that the content prefetched to-said instruction buffer has changed on said main storage; and invalidating means (79, 222) for invalidating the content of said instruction buffer in response to the detection by said detection means that the execution of the instruction has proceeded to the changed instruction.
Claim 3
Dependent Claim
179 words
A data processing system according to Claim 1 wherein said detection means includes holding means (52, 53) for holding said store address and said second information, first detection means (55) for detecting that the content prefetched to said instruction buffer has been changed on said main storage and second detection means (64) for detecting that the execution of the instruction has proceeded to the changed instruction, said holding means holding the store address by the store instruction and the second information each time when said first detection means detects the changing, said first detection means detecting the changing based on said instruction fetch address, said store address by the store instruction and said execution instruction address, and, once it has detected the changing, detecting the further changing based on said instruction fetch address, said store address by the store instruction and the store address held in said holding means, and said second detection means detecting the proceeding based on said execution instruction address, said first information and the store address and the second information held in said holding means.
Claim 4
Dependent Claim
21 words
A data processing system according to Claim 2 wherein said suppression means responds to the detection by said first detection means.
Claim 5
Dependent Claim
23 words
A data processing system according to Claim 3 or 4 wherein said invalidating means responds to the detection by said second detection means.
Claim 6
Dependent Claim
72 words
A data processing means according to Claim 2 wherein said detection means further includes third detection means (60) for detecting that the next instruction to said store instruction has been changed on said main storage, based on said store address by said store instruction, said second information, said execution instruction address and said first information, said invalidating means responding to the detections by said second detection means and said third detection means.
Claim 7
Dependent Claim
57 words
A data processing system according to Claim 2 or 5 further comprising bistable means (71) which is set in response to the detection by said first detection means and reset in response to the invalidation of said instruction buffer, an output of said bistable means suppressing the instruction prefetch from said main storage to said instruction buffer.
Claim 8
Dependent Claim
72 words
A data processing system according to Claim 6 further comprising selection means (56) for selectively supplying one of said instruction fetch address and the store address held in said holding means to said first detecting means, said selection means selecting said instruction fetch address when said bistable means is in a reset state and selecting the store address held in said holding means when said bistable means is in a set state.
Claim 9
Dependent Claim
24 words
A data processing system according to Claim 6 wherein said second detection means is enabled when said bistable means is in the set state.
References Cited (Backward Citations)
No citation records indexed.
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