Electron-beam lithographic apparatus

Claim 1

In an electron beam lithographic apparatus suitable for drawing patterns on an object, whereby the surface of the object is divided into a number of sections, each representing the area which can be scanned by the electron beam, the pattern to be drawn in a given section is decom- osed into a plurality of partial patterns such that the section pattern can be built up from the partial patterns by operating thereon with one or a combination of logical operators, the partial patterns being specified by co-ordinates relative to an orthogonal co-ordinate system on the surface of the object, and the partial pattern co- ordinate data are converted to produce bit patterns stored in pattern memory means, each bit pattern corresponding to a respective partial pattern, but being in a form suitable as input to an electron beam blanking device, an electron beam blanking control system comprising: -means (11, 13a-13c) for generating address data corresponding to a plurality of partial patterns, -pattern memory means (15a-15c, 16a-16c) comprising a plurality of memory storage locations, each specified by an address datum from said address data generating means, for storing bit patterns corresponding to said partial patterns, and -means (20) for effecting blanking of an electron beam according to the bit patterns to thereby draw a pattern on an object, characterized in that -the said means for generating address data includes pattern co-ordinate data memory means (11), in which co-ordinate data of partial patterns of a pattern to be drawn are stored, and a plurality of data converting means (13a-13c), each data converting means being suitable to receive from said pattern co-ordinate data memory means the co-ordinate data for one partial pattern and for converting said co-ordinate data into the respective address data, -a plurality of reading means (18a-18c), equal in number to the number of data converting means (13-13c), is provided for synchronously reading out said bit patterns from said pattern memory means (15a-15c, 16a-16c), -synthesizing means (19), comprising one or a combination of logical operating means, is provided for synthesizing said bit patterns read out from said pattern memory means (15a-15c, 16a-16c) by said reading means (18a-18c) to produce a resultant bit pattern, and -said pattern memory means is constituted by a plurality of paired memories (15a, 16a-15c, 16c), each memory pair being connected to a respective data converting means (13a-13c) and to a respective reading means (18a-18c) via respective switching means (14a-14c, 17a-17c) in such a way that one bit pattern is written to one memory of each memory pair while a previously written bit pattern is being read out from the other memory of the said memory pair.