Logic structure utilizing polycrystalline silicon Schottky diode

Claim 2

An integrated circuit structure characterized by: a region of semiconductor material electrically isolated from surrounding regions by a region of insulating material, the region of semiconductor material containing at least one transistor; at least one Schottky diode formed on the region of insulating material and connected to the at least one transistor; and at least one resistor formed on the region of insulating material and connected to the at least one transistor.

Claim 3

A structure as in claim 1 characterized in that each said transistor includes a base, a collector and at least one emitter, and each said Schottky diode is connected to the collector.

Claim 4

A structure as in claim 1 or 2 characterized in that said resistor is connected to the base.

Claim 5

A structure as in claim 3 characterized in that: a source of electrical potential is also connected to said resistor; an input signal is supplied to said base; and an output signal is obtained from each said Schottky diode. ,

Claim 6

A structure as in any previous claim characterized in that a layer of semiconductor material is formed outside said region of semiconductor material and above said region of insulating material.

Claim 7

A structure as in any previous claim characterized in that said insulating material is an oxide of said region of semiconductor material.

Claim 8

A structure as in claim 5 or 6 characterized in that said Schottky diode comprises the interface between the layer of semiconductor material and an overlying electrically conductive layer.

Claim 9

A structure as in claim 7 characterized in that said layer of semiconductor material comprises polycrystalline silicon, and said polycrystalline silicon is deposited on a lower conducting layer of metal silicide.

Claim 10

A structure as in claim 8 characterized in that said metal silicide is a refractory metal silicide.

Claim 11

A structure as in claim 7, 8 or 9 characterized in that said overlying electrically conductive layer comprises a metal.

Claim 12

A structure as in any one of claims 5-10 characterized in that said resistor comprises a portion of the layer of semiconductor material formed outside said region of semiconductor material and above said insulating material.

Claim 13

A structure as in claim 11 characterized in that the portion of the layer of polycrystalline silicon comprising said resistor is more lightly doped with an impurity than the surrounding polycrystalline silicon.

Claim 14

An integrated circuit structure characterized by: an epitaxial pocket of semiconductor material containing a bipolar transistor and being surrounded by oxidized semiconductor material; a layer of a metal silicide disposed on a first region of the oxidized semiconductor material outside the epitaxial pocket; a first layer of polycrystalline silicon disposed only on the layer of metal silicide; a second layer of polycrystalline silicon disposed over the first layer over the epitaxial pocket and over a second region of the oxidized semiconductor material, a first portion of the second layer overlying the first region and a second portion of the second layer overlying the second region, said first portion and said second portion being more lightly doped with an impurity than the remaining portions of the second layer, the remaining portions of the second layer electrically connecting the layer of metal silicide to the bipolar transistor and separately electrically connecting the second portion to the bipolar transistor; and means for providing ohmic connections to each of the bipolar transistor, said first portion and said second portion. -

Claim 15

An integrated circuit structure characterized by: an epitaxial pocket of semiconductor material containing a bipolar transistor and being surrounded by oxidized semiconductor material; a layer of a metal silicide disposed on a first region of the oxidized semiconductor material outside the epitaxial pocket; a first layer of polycrystalline silicon disposed only on the layer of metal silicide; a second layer of polycrystalline silicon disposed over the first layer over the epitaxial pocket and over a second region of the oxidized semiconductor material, a first portion of the second layer overlying the first region and a second portion of the second layer overlying the second region, said first portion and said second portion being more lightly doped with an impurity than the remaining portions of the second layer, the remaining portions of the second layer electrically connecting the layer of metal silicide to the bipolar transistor and separately electrically connecting the second portion to the bipolar transistor; and means for providing ohmic connections to each of the bipolar transistor, said first portion and said second portion. -

Claim 16

A structure as in claim 13 characterized in that said bipolar transistor includes a base, a collector, and at least one emitter.

Claim 17

A structure as in claim 14 characterized in that: said first portion of the second layer is connected to the collector; and said second portion of the second layer is connected to the base.

Claim 18

A structure as in claim 14 or 15 characterized in that said bipolar transistor includes a first and second emitter, said first emitter being grounded and said second emitter being connected to the base.

Claim 19

A structure as in claim 13, 14, 15 or 16 characterized in that each of said first and said second layer of polycrystalline silicon is doped with N conductivity type impurity.

Claim 20

A structure as in claim 13, 14, 15, 16 or 17 characterized in that said bipolar transistor is an NPN transistor.

Claim 21

A process for fabricating an integrated circuit characterized by: fabricating a pocket of semiconductor material surrounded by insulating material; depositing a layer of a metal silicide on a first region of the insulating material; depositing a first layer of semiconductor material on the layer of metal silicide; and forming selected portions of a second layer of semiconductor material over at least a second region of said insulating material, said first layer of semiconductor material, and selected portions of the pocket, at least those portions of the second layer extending from the first layer to said pocket and from said pocket to the second region having higher impurity doping than that portion of said second layer overlying said second region.

Claim 22

A process for fabricating an integrated circuit characterized by: fabricating a pocket of semiconductor material surrounded by insulating material; depositing a layer of a metal silicide on a first region of the insulating material; depositing a first layer of semiconductor material on the layer of metal silicide; and forming selected portions of a second layer of semiconductor material over at least a second region of said insulating material, said first layer of semiconductor material, and selected portions of the pocket, at least those portions of the second layer extending from the first layer to said pocket and from said pocket to the second region having higher impurity doping than that portion of said second layer overlying said second region.

Claim 23

A process as in claim 19 characterized in that: said insulating material comprises oxidized silicon; and said first and said second layers of semiconductor material comprise silicon.

Claim 24

A process as in claim 20 characterized in that said first and said second layers comprise polycrystalline silicon.

Claim 25

A process as in claim 19, 20 or 21 characterized in that said step of forming selected portions of a second layer comprises: depositing lightly doped semiconductor material; doping those portions of said second layer which have a higher impurity doping; and removing undesired regions of said second layer.

Claim 26

A process as in claim 22 characterized in that said second layer is deposited over all of the pocket and said insulating material and then removed from over part of said pocket.

Claim 27

A process as in-claim 19, 20, 21, 22, or 23 characterized by the step of fabricating at least one transistor in the pocket.

Claim 28

A process as in claim 24 characterized in that a third region of the second layer is separated from said pocket by said second region of said second layer.

Claim 29

A process as in claim 25 characterized by the step of fabricating electrical connections to said third region, said transistor , and said first layer of semiconductor material.

Claim 30

A process as in any one of claims 19-26 characterized in that said first layer of semiconductor material is more heavily doped than said portion of said second layer overlying said second region.