A digital waveform conditioning circuit

Claim 2

A digital waveform conditioning circuit which comprises: an input terminal (10) for receiving a signal (2B) deformed from a digital rectangular signal (2A), said deformed digital signal having alternating positive and negative cycles; means (17 to 24) for generating a reference signal (Vr) produced by combining positive and negative components rectified from the positive and negative cycles of the deformed digital signal; means (11) for comparing said deformed digital signal with said reference signal; means (26) for holding an output signal (2C) of said comparing means for a period controlled by a clock signal (R-CK) synchronising said output signal with said original rectangular signal; and an output terminal (28) for receiving the output signal from said holding means.

Claim 3

A digital waveform conditioning circuit according to claim 1, wherein said holding means (26) has inverted and non-inverted outputs (Q and Q) and wherein said reference signal generating means comprises individual means (19 and 20) for sampling the positive and negative cycles of said deformed digital signal(2B) under the control of said inverted and non-inverted outputs of said holding means.

Claim 4

A digital waveform conditioning circuit according to claim 2, wherein said individual sampling means comprise first and second analogue switching means (19 and 20) each having a pair of main current-carrying terminals and a control terminal, the control terminals being individually connected to different ones of said inverted and non-inverted outputs (Q and Q) and wherein said reference signal generating means further comprises: first and second diodes (17 and 18) connected between said input terminal (10) and individual ones of said pair of current-carrying terminals, said diodes being connected in opposite polarity with one another to said input terminal; first and second capacitors (21 and 22) individually connected between the other ones of said pair of current-carrying terminals and ground for storing voltages applied by said-first and second analogue switching means; and first and second resistors (23 and 24) each having one terminal connected to individual ones of said capacitors and theirother terminals being connected together for combining voltages stored by first and second capacitors, said combined voltages forming said reference signal (Vr).

Claim 5

A digital waveform conditioning circuit according to any one of claims I to 3, wherein said holding means (26) is a "D" type flip-flop.