Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
104 words
1 . Apparatus for assisting fault-finding in a data processing system (10) having a target CPU (11 or 41) and a program under test, characterised in that the apparatus includes monitoring means (16) for detecting and recording data input and interrupt signals applied to the CPU (11 or 41) during program execution and derived from external stimuli, counting means (21) for measuring and recording the occurrence time of such signals relative to the CPU's time frame and means for replaying the program under. test (30 or 48) in synchronous combination with the recorded data input and interrupt signals applied at appropriate relative occurrence times.
Claim 2
Dependent Claim
104 words
1 . Apparatus for assisting fault-finding in a data processing system (10) having a target CPU (11 or 41) and a program under test, characterised in that the apparatus includes monitoring means (16) for detecting and recording data input and interrupt signals applied to the CPU (11 or 41) during program execution and derived from external stimuli, counting means (21) for measuring and recording the occurrence time of such signals relative to the CPU's time frame and means for replaying the program under. test (30 or 48) in synchronous combination with the recorded data input and interrupt signals applied at appropriate relative occurrence times.
Claim 3
Dependent Claim
17 words
Apparatus according to claim 1 characterised in that the target CPU (11 or 41) is a microprocessor.
Claim 4
Dependent Claim
36 words
Apparatus according to claim 1 characterised in that the counting means (21) is arranged to count CPU instruction fetch events and to record the instantaneous count thereof at detection of each data input and interrupt signal.
Claim 5
Dependent Claim
36 words
Apparatus according to claim 3 characterised in that the monitoring means (16) and counting means (21) are responsive to data input and interrupt signals and instruction fetch events respectively occurring on the target CPU bus (14).
Claim 6
Dependent Claim
28 words
Apparatus according to claim 4 characterised in that the monitoring means (16) includes means for generating and recording a respective event code for each type of information recorded.
Claim 7
Dependent Claim
40 words
-Apparatus according to claim 3, 4 or 5 characterised in that the apparatus includes a backing store (22, 31 or 47) for storing sequentially each data input or interrupt signals together with an appropriate respective event code and instantaneous count.
Claim 8
Dependent Claim
38 words
70 Apparatus according to claim 6 characterised in that the means for replaying the program under test includes a host computer (48) arranged by means of a simulator program to provide means for replaying the program under test.
Claim 9
Dependent Claim
47 words
80 Apparatus according to claim 7 characterised in that the simulator-programmed host computer (48) has an initial state file for recording the initial state of the target CPU (11) when containing the program under test and a data file for recording sequentially data input and interrupt events.
Claim 10
Dependent Claim
54 words
Apparatus according to claim 8 characterised in that the monitoring means and the counting means are provided by a bus monitor unit (included in ARM 43) incorporating an instruction fetch counter, the bus monitor unit being arranged to record an event code, a data word, an address and an event count for monitored events.
Claim 11
Dependent Claim
56 words
Apparatus according to claim 9 characterised in that there is provided a data reduction device (included in ARM 43) responsive to the bus monitor unit and arranged to store any sequence of identical data inputs by storing one such input and incrementing the event count appropriately to indicate the number of data inputs in the sequence.
Claim 12
Dependent Claim
49 words
Apparatus according to claim 10 characterised in that there is provided a data transmission device being operative to transmit to the backing store 47 event information comprising data input signals from the data reduction device and interrupt signals from the bus monitor unit together with the corresponding event count.