EP0062165A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Multiprocessors including private and shared caches
Assignee: International Business Machines Corp
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Filing: 1982-03-04
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Granted: —
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Expires: 2002-03-04
Abstract
Abstract In a multiprocessor, each processor (4, 6) has its own high speed store in buffer (SIB) cache (8, 24) and each processor shares a common cache (10) with the other processors direct data paths (14, 28) interconnecting the common cache and the private caches. The control system ensures that all processors access the most up-to-date copy of memory information with a minimal performance impact, allowing only read only copies of the same shared memory block (line) to exist simultaneously in all private caches. Lines that are both shared and changed are stored in the common shared cache, which each processor can directly fetch from and store into. In a general system the cache manager dynamically detects and moves lines, which are both shared and changed, over direct interconnecting data paths (14, 25) to the common shared cache and returning, by cast out, lines from the shared cache once sharing has most probably ceased. A simplified system for structured applications is disclosed.
Inventors
- 👤 Robert Percy Fletcher
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 17:17
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/084
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
93 words
Data processing apparatus including multiple processors (4, 6) each having its own private cache (8, 24) and sharing main memory and a cache management facility characterized in that there is included, in addition, a shared common cache (10) related to the cache management facility in such a way that shared changed lines (blocks, pages or any other term that may be used to refer to the cache transferable units of data) are permitted to exist only in the common cache, any multiple copies of lines in the private caches being maintained "read only".
Claim 2
Dependent Claim
93 words
Data processing apparatus including multiple processors (4, 6) each having its own private cache (8, 24) and sharing main memory and a cache management facility characterized in that there is included, in addition, a shared common cache (10) related to the cache management facility in such a way that shared changed lines (blocks, pages or any other term that may be used to refer to the cache transferable units of data) are permitted to exist only in the common cache, any multiple copies of lines in the private caches being maintained "read only".
Claim 3
Dependent Claim
85 words
Data processing apparatus as claimed in claim 1 designed to operate in relation to data files having a balanced structure of read only lines (say instruction modules) and potentially writeable lines (say operand, or mixed instruction/operand modules) wherein the caches (590, 592, 594) are interconnected only indirectly via main memory (598) and the cache management facility (596) is arranged to overwrite read only lines on demand into the private cache of the requester and to load potentially writeable lines into the shared cache (594) only.
Claim 4
Dependent Claim
93 words
Data processing apparatus as claimed in claim 1 designed to handle applications of no specific structure (a general purpose multiprocessor) in which the private caches (8, 24) have independent direct data paths (14, 28) to the shared cache (10) and the cache management facility (38) dynamically detects and moves, from the private cache(s) into the shared cache, those lines which are both shared and changed, over the direct data paths, writing back, as necessary, a corresponding number of those lines therein which are, most probably, no longer shared, into common main memory (36).
Claim 5
Dependent Claim
24 words
Data processing apparatus as claimed in claim 3 wherein the cache management facility marks all privately contained copies of shared unchanged lines "read only".
Claim 6
Dependent Claim
90 words
Data processing apparatus as claimed in claim 4 in which the cache management facility maintains a line residence table (20, 22, 24) for each cache recording not only system line address and corresponding cache line address but also status (validity, change, permitted type of access and potential replacement order), the residency being searched in the tables and being a function of status as well as of address correspondence so that, for example, a write access request to a private cache contained read only line registers as a miss i.e. non-residency.
Claim 7
Dependent Claim
135 words
Data processing apparatus as claimed in claim 5 wherein the search pattern until a hit is private cache, directly followed by shared cache directory, followed by remote cache directory (ies) followed by main memory (which must succeed), a hit in either of the first two directories granting access to the associated cache, a hit in the (or any) remote cache directories resulting in the hit line being copied into the shared cache and access thereto granted if its status is changed, any private cache copy being imemdiately subsequently given invalid status, or, if its status is unchanged, the fetching of the line from main memory into the requestors private cache with a read only status entry in the corresponding directory, the status for that line in any remote directory being also set to read only.
References Cited (Backward Citations)
No citation records indexed.
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