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EP0062097A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

Method of displaying the logic status of several neighbouring modes in integrated circuits in a logic picture by using a pulsed-electron probe

Assignee: ICT Integrated Circuit Testing Gesellschaft fuer Halbleiterprueftechnik mbH
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Filing: 1981-10-20
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Granted: —
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Expires: 2001-10-20
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Abstract

Abstract Translated from German Um logische Zustandsänderungen mehrerer benachbarter Schaltungsknoten in integrierten Schaltungen in einem Logikbild mittels einer gepulsten Elektronensonde auch an kurzen Leitbahnstücken darstellen zu können, tastet die gepulste Elektronensonde auf der integrierten Schaltung stets dieselbe Strecke in x-Richtung ab, wobei die Phase der Elektronenpulse bei jedem neuen so beschaffenen Abtastvorgang kontinuierlich verschoben wird. Dabei kann bis zur Aufnahmelinie die Probe abgebildet werden und erst bei dieser Aufnahmelinie die y-Ablenkung der gepulsten Elektronensonde festgehalten werden. In order to be able to represent logical changes in the state of several neighboring circuit nodes in integrated circuits in a logic image by means of a pulsed electron probe even on short sections of the interconnect, the pulsed electron probe on the integrated circuit always scans the same distance in the x direction, the phase of the electron pulses being the same with each new one procurement is continuously shifted. The sample can be imaged up to the acquisition line and the y-deflection of the pulsed electron probe can only be recorded at this acquisition line.

Inventors

  • 👤 Peter Dipl.-Ing. Fazekas
  • 👤 Hans-Peter Dr. Feuerbaum
  • 👤 Ulrich Dipl.-Phys. Knauer
  • 👤 Johann Ing.Grad. Otto

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-30 19:19
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/302; G01R31/305; B; B82; B82Y; B82Y15/00

Claims Analysis

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References Cited (Backward Citations)

DE2813948A1 Cited
DE2814049A1 Cited

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