EP0060388A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Data processing apparatus including a peripheral processing complex
Assignee: International Business Machines Corp
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Filing: 1982-02-10
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Granted: —
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Expires: 2002-02-10
Abstract
Abstract A data processing system incorporating a controlling processor (12) together with plural devices (2, 4, 6, 8, 10) intercommunicating via shared memory 16, such intercommunication being independent of but initialized by the controlling processor, wherein intercommunication control is exercised by the combination of (a) a pointer table 20, the pointers in which are set by the controlling processor, are addressable by the devices and are indexed routinely in use, (b) table entry identifier initialization in the devices by the controlling processor, (c) control code (A CODE; P CODE) exchange between intercommunicating devices, independently of the shared memory, enabling access to the pointer table, and (d) the pointers, as accessed, providing selective access to the shared memory.
Inventors
- 👤 Yutaka Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 01:26
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/32; H04N1/32561; H04N1/32566; G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F15/00; G06F15/16; G06F15/163; G06F15/167
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
197 words
A data processing system having a shared memory (16), a processor (12); a plurality of functional devices (2, 4, 6, 8, 10); a random access memory (16) providing at least one shared buffer area for data transfer between said functional devices; and shared memory access means (18) therefor, characterized in that the shared memory access means includes a pointer table (20) having a plurality of entries each capable of retaining an address of said shared buffer area, and controlling writing from a selected functional device into said shared buffer area and reading from said shared buffer area into another selected functional device; said functional devices having means for generating one or more control codes (ACODE,PCODE) representing access statuses of said shared buffer area; said processor initializing, in response to a data transfer request from a certain functional device, said pointer table and more than one functional devices involved in said data transfer request; said more than one functional devices, after being initialized by said processor, autonomously transferring data therebetween through said shared buffer area by interchanging said control codes with each other and accessing said pointer table based thereon under control of said shared memory access means.
Claim 2
Dependent Claim
197 words
A data processing system having a shared memory (16), a processor (12); a plurality of functional devices (2, 4, 6, 8, 10); a random access memory (16) providing at least one shared buffer area for data transfer between said functional devices; and shared memory access means (18) therefor, characterized in that the shared memory access means includes a pointer table (20) having a plurality of entries each capable of retaining an address of said shared buffer area, and controlling writing from a selected functional device into said shared buffer area and reading from said shared buffer area into another selected functional device; said functional devices having means for generating one or more control codes (ACODE,PCODE) representing access statuses of said shared buffer area; said processor initializing, in response to a data transfer request from a certain functional device, said pointer table and more than one functional devices involved in said data transfer request; said more than one functional devices, after being initialized by said processor, autonomously transferring data therebetween through said shared buffer area by interchanging said control codes with each other and accessing said pointer table based thereon under control of said shared memory access means.
Claim 3
Dependent Claim
50 words
A data processing system as claimed in claim 1, wherein said processor loads a start address of said shared buffer area into selected entries of said pointer table and sends identifiers of said selected entries and data transfer control information to said more than one functional devices during the initialization.
Claim 4
Dependent Claim
46 words
A data processing system as claimed in claim 2, wherein said data transfer control information includes device addresses of functional devices to or from which data are transferred, and said more than one functional devices interchange said control codes with each other using said device addresses.
Claim 5
Dependent Claim
67 words
A data processing system as claimed in any one of claims 1 through 3, wherein said shared memory access means comprises means for controlling reading and writing of said pointer table and address counter means (22) for sending an address read out of a selected entry of said pointer table to said memory, incrementing said address by one and returning said incremented address to said selected entry.
Claim 6
Dependent Claim
29 words
A data processing system as claimed in claim 4, wherein said reading of said pointer table is performed by one of said identifiers sent from a selected functional device.
Claim 7
Dependent Claim
54 words
A data processing system as claimed in claim 5, wherein each of said more than one functional devices sends a request to said shared memory access means before outputting one of said identifiers or said control codes and outputs said one of said identifiers or said control codes only when said request is granted.
Claim 8
Dependent Claim
41 words
A data processing system as claimed in claim 6, wherein said control codes include a first code representing that said shared buffer area is available for writing and a second code representing that said shared buffer area is available for reading.
Claim 9
Dependent Claim
40 words
A data processing system as claimed in claim 7, wherein each of said more than one functional devices is defined as an upstream device writing into said shared buffer area or a downstream device reading from said shared buffer area.
Claim 10
Dependent Claim
63 words
A data processing system as claimed in claim 8, wherein said shared buffer area is logically divided into a plurality of segments, said downstream device sends said first code to said upstream device so far as one or more segments are empty, and said upstream device sends said second code to said downstream device every time one of said segments has been written.
Claim 11
Dependent Claim
37 words
A data processins system as claimed in claim 9, wherein said upstream device generates a write request in response to said first code and said downstream device generates a read request in response to said second code.
References Cited (Backward Citations)
No citation records indexed.
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