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EP0059236A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Method and arrangement for addressing translation look-aside buffers

Assignee: Siemens AG
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Filing: 1981-10-13
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Granted: —
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Expires: 2001-10-13
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Abstract

Abstract 1. A method for addressing address conversion stores (ATM A, ATM B, ATM C) which convert the logic address space of a virtual store, which is divided into a plurality of segments each of which has a plurality of pages, into the physical address space of the main store, employing two address conversion stores (ATM A, ATM B) which are of identical size and of a first type and which are addressed by the same portions of the segment component (SEG) and the page component (SE) of the virtual address and transmit a real page address (SA), and employing an address conversion store (ATM C) of a second type which is addressed by the segment component (SEG) of the virtual address and transmits a real page table address (STA) which is added to the page component of the virtual address and allows the addressing of a page table which is present in the main store and contains real page addresses, characterised in that in order to address the address conversion store (ATM C) of a second type the n highest-value bits of the segment component (SEG) of the virtual address is modified by means of n programme character bits (PID 0, 1, 2) in such a manner that each of the 2**n programmes is assigned one of 2**n areas within the address conversion store, and that in order to address both address conversion stores (ATM A, ATM B) of a first type which are respectively divided into 2**m areas, on the one hand the m=n-1 higher-value bits of the page component (SE) of the virtual address are modified by means of m=n-1 programme character bits (PID 1, 2) and on the other hand there is provided an alternating bit store (RAM-ALT) which can be addressed similarly to the two address conversion stores of a first type and whose read-out alternating bit controls in alternating manner one of the two address conversion stores (ATM A, ATM B) of a first type and is re-read into the alternating bit store in an inverted form under the same address.

Inventors

  • 👤 Jürgen Dipl.-Ing. Bethmann

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-08 22:01
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1036

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