EP0058795A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Wait circuitry for interfacing between field maintenance processor and device specific adaptor circuit
Assignee: Genrad Inc
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Filing: 1981-10-23
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Granted: —
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Expires: 2001-10-23
Abstract
Abstract A field maintenance processor including a microprocessor that effects transparent refreshing ef a-dynamic memory includes a counter circuit which times the duration of the «wait» signal produced by a slow memory or a slow peripheral device accessed by the processor. The counter circuit produces a «wait enable» signal which enables the «wait» signal to produce an «enabled wait» signal that is conducted to a wait input of the processor for only a predetermined time, to ensure transparent refreshing of the entire dynamic memory. If the «wait» signal produced by the slow memory device has not ceased when the predetermined time has elapsed, the «wait enable» signal disappears, causing the »enabled wait» signal also to disappear. The disappearance of the «wait enable» signal also causes a «wait interrupt» signal to be generated and transmitted to the microprocessor, resulting in execution of an interrupt routine to determine which instruction execution was earlier halted in response to the «enabled wait» signal. The entire dynamic memory is transparently refreshed during execution of the interrupt routine.
Inventors
- 👤 Edward Harry Greenwood
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 04:30
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
261 words
In a system including a dynamic random access memory and a processor which automatically effects transparent refresh operations on said dynamic random access memory during execution of program instructions in order to ensure refreshing of all locations of said dynamic random access memory, the improvement comprising in combination: (a) counting means for counting from a first count to a second count in response to a first wait signal and producing a wait enable signal if said second count is attained by said counting means; (b) a first wait signal conductor for conducting said first wait signal from a slow memory circuit which has been addressed by said processor, said slow memory circuit being required to generate said first wait signal if the access time of said slow memory circuit exceeds a predetermined amount of time; (c) count initiating means coupled between said counting means and said first wait signal conductor for responding to said first wait signal to initiate said counting; (d) interrupt signal producing means responsive to said counting means for producing an interrupt signal in response to attaining of said second count by said counting means and applying said interrupt signal to said processor; (e) enabled wait signal producing means responsive to said wait enable signal and said first wait signal for producing an enabled wait signal and applying said enabled wait signal to a wait input of said processor; (f) said processor including means for responding to said interrupt signal by executing a wait interrupt routine resulting in refreshing of all locations of said dynamic random access memory.
Claim 2
Dependent Claim
261 words
In a system including a dynamic random access memory and a processor which automatically effects transparent refresh operations on said dynamic random access memory during execution of program instructions in order to ensure refreshing of all locations of said dynamic random access memory, the improvement comprising in combination: (a) counting means for counting from a first count to a second count in response to a first wait signal and producing a wait enable signal if said second count is attained by said counting means; (b) a first wait signal conductor for conducting said first wait signal from a slow memory circuit which has been addressed by said processor, said slow memory circuit being required to generate said first wait signal if the access time of said slow memory circuit exceeds a predetermined amount of time; (c) count initiating means coupled between said counting means and said first wait signal conductor for responding to said first wait signal to initiate said counting; (d) interrupt signal producing means responsive to said counting means for producing an interrupt signal in response to attaining of said second count by said counting means and applying said interrupt signal to said processor; (e) enabled wait signal producing means responsive to said wait enable signal and said first wait signal for producing an enabled wait signal and applying said enabled wait signal to a wait input of said processor; (f) said processor including means for responding to said interrupt signal by executing a wait interrupt routine resulting in refreshing of all locations of said dynamic random access memory.
Claim 3
Dependent Claim
63 words
The system of Claim 1 wherein said counting means ' includes a counter having a load input for effecting loading of said first count into said counter, a clear input for effecting clearing of said counter, a carry output for producing a carry signal when said second count is contained in said counter, and an enable input for enabling said counter to count.
Claim 4
Dependent Claim
31 words
The system of Claim 2 wherein the time required for said counter to count from said first count to said second count is substantially equal to said predetermined amount of time.
Claim 5
Dependent Claim
86 words
The system of Claim 2 wherein said count initiating means includes an output coupled to said load input, said counter beginning incrementing if said load input goes from a logical "zero" level to a logical "one" level, said counter loading said second count into said counter if said load input goes from said logical-"one" level to said logical "zero" level, said output of said counter initially going to said logical "one" level if said first wait signal goes from a logical "zero" to a'logical "one" level.
Claim 6
Dependent Claim
20 words
The system of Claim 4 wherein said counting means produces said wait enable signal in response to said carry signal.
Claim 7
Dependent Claim
46 words
The system of Claim 5 wherein said counting means causes said wait enable signal to be at a logical "one" if said carry signal is at a logical "zero" level and at a logical "zero" level if said carry signal is at a logical "one" level.
Claim 8
Dependent Claim
56 words
The system of Claim 6 wherein said enabled wait signal producing means causes said enabled wait signal to be at a logical "one" level if said access time is substantially less than said predetermined amount of time and at a logical "zero" level if said access time is substantially greater than said predetermined amount of time.
Claim 9
Dependent Claim
28 words
The system of Claim 7 wherein said counting means produces an enable signal and applies said enable signal to said enable input when said carry signal is present.
Claim 10
Dependent Claim
21 words
The system of Claim 8 wherein said interrupt signal producing means includes a parallel input-output circuit that produces said interrupt signal.
Claim 11
Dependent Claim
32 words
The system of Claim 9 wherein said processor produces a clear signal in response to said interrupt signal, and effects transmitting of said clear signal to said clear input of said counter.
References Cited (Backward Citations)
No citation records indexed.
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