Multiplexer for single-octave data processor

Claim 2

Multiplexing means for allowing multi-octave processing by means of a single octave data processor and comprising: means for progressively delaying sampled data, corresponding to delay-ceding thereof; and multiplex means for sampling progressively delayed delay-ooded data at progressively reduced data sampling rates, corresponding to lower octaves of interest.

Claim 3

The device of Claim 1 in which there is further provided output multiplex means responsive to said single octave processor and operated in unison with said multiplex sampling means for sorting out the sampled output of said single octave processor by octaves of interest.

Claim 4

The device of Claim 1 in which said multiplexing means allows five-octave processing by means of the oommon single-octave processor, and in which: said sampled input data is applied to a multiplex input line 1; said means for progressively delaying provides delay-coding of 0, 1, 3, and 7 word times, respectively, corresponding to multiplex input lines 2, 3, 4 and 5, respectively; and said multiplex means for sampling samples said data input lines in the following sequence, 1, 2, 1, 3, 1, 2, 4, 1, 2, 1, 3, 2, 1, 5, 1, 2, 1, 3, 1, 2, 1, 4, 1, 2, 1, 3, 1, 2, 1.

Claim 5

The device of Claim 1 in which said multiplexing means allows five-octave processing by means of the common single-octave processor, and in which: said sampled input data is applied to a multiplex input line 1; said means for progressively delaying provides delay-coding of 0, 1, 3 and 7 sample times (T), respectively; corresponding to multiplex input lines 2, 3, 4 and 5, respectively; and said multiplex means for sampling performs sampling of said multiplex input line 1 during a first portion of each sample-time, and samples one. of multiplex input lines 2-5 during a second portion of each sample time (T) in accordance with the following sequence: 2, 3, 2, 4, 2, 3, 2, 5, 2, 3, 2, 4, 2, 3, 2.

Claim 6

The device of Claim 1 in which said multiplexing means allows N-octave processing by means of the common single-octave processor, and in which: said sampled input data is applied to a multiplex input line 1; said means for progressively delaying provides delay-coding DT=τ (for sanple time, T) in accordance with the relationship, D = 2 N-2 -1, where N is an integer number; and said multiplex means for sampling samples said input data line 1 during a first portion of each sample time, T, and sanples one of said progressively delay-coded samples during a second portion of said sanple time in accordance with the following set of sequences: S(N-1), S(N), S (N-1), where S(l) = 1.

Claim 7

Multiplexed single octave means for processing multi-octave data, comprising: two-pole sampling means for sampling input data and feedback data, alternatively, each at a preselected sampling periodicity; a single-octave discrete time data processor; a discrete-time, anti-aliasing low pass filter, an input of each of said processor and filter being commonly connected to an output of said sampling means; feedback multiplex delay means interposed between an output of said filter and a feedback input of said sampling means for providing interleaved output sample sequences represented by successively delay-coded and decimated sampled data, a successive delayed sequence having a progressively doubled sampling periodicity corresponding to a progressively lower octave; each of said filter and said processor including like multiplex delay means as said feedback multiplex delay means for providing interleaved output sample sequences representing progressively delay-coded and decimated sampling rates, a successive delayed sequence having a progressively doubled sampling periodicity corresponding to a progressively lower octave, all said multiplex delay means operated in unison; and multiplex output means responsively coupled to an output of said processor for sorting out the outputs of said processor by preselectively delay-coded and decimated sequences of output samples on a sequence of output line sets, each set corresponding to a mutually exclusive octave of interest.

Claim 8

Multiplexed single octave means for processing multi-octave data, comprising: two-pole sampling means for sampling input data and feedback data, alternatively, each at a preselected sampling periodicity; a single-octave discrete time data processor; a discrete-time, anti-aliasing low pass filter, an input of each of said processor and filter being commonly connected to an output of said sampling means; feedback multiplex delay means interposed between an output of said filter and a feedback input of said sampling means for providing interleaved output sample sequences represented by successively delay-coded and decimated sampled data, a successive delayed sequence having a progressively doubled sampling periodicity corresponding to a progressively lower octave; each of said filter and said processor including like multiplex delay means as said feedback multiplex delay means for providing interleaved output sample sequences representing progressively delay-coded and decimated sampling rates, a successive delayed sequence having a progressively doubled sampling periodicity corresponding to a progressively lower octave, all said multiplex delay means operated in unison; and multiplex output means responsively coupled to an output of said processor for sorting out the outputs of said processor by preselectively delay-coded and decimated sequences of output samples on a sequence of output line sets, each set corresponding to a mutually exclusive octave of interest.

Claim 9

The device of Claim 6 in which each of said multiplex delay means comprises: a clocked shift register for providing a plurality of progressively delays to an applied input; a multiplexed switch for sanpling said applied input and said delayed input in a preselected sequence, as to achieve a plurality of data sequence, each of a progressively-doubled sampling periodicity, each successive periodicity being preselectively delay-coded; and a logic decoder responsive to a clocked counter for controlling said preselected sanpling sequence of said multiplexed switch.

Claim 10

The device of Claim 7 in which said multiplexed switch means includes said two-pole sampling means.