EP0055570A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Logic circuit
Assignee: Fujitsu Ltd
•
Filing: 1981-12-21
•
Granted: —
•
Expires: 2001-12-21
Abstract
Abstract A logic circuit has a first logic gate (G 6 ), having a plurality of inputs (a and b) and an output (m), and a second logic gate comprising a driving FET (Q 6 ) and a plurality of load FET's (T 6 ' and T 6 ). The gate of the driving FET (Q 6 ) is connected to the output (m) of the first logic gate and the gates of the load FET's (T 6 ' and T s ) are connected to respective inputs (a, b) of the first logic gate. The driving FET and the load FET's are connected in series. A pair of FET's (T', T), one depletion-mode and one enhancement-mode, with their drains, sources and gates respectively connected in common may be used in place of a single load FET.
Inventors
- 👤 Koichi Nishiuchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 01:38
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09441; H03K19/09443; H03K19/09445; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
159 words
A logic circuit comprising: first logic gate means, comprising at least one logic gate circuit having a plurality of logical input terminals, and second logic gate means, comprising at least one logic gate circuit to which a logical output signal of the first logic gate means is applied, the second logic gate means having at least one driving field-effect transistor (FET), and load FET's at least equal in number to the logical input terminals of the first logic gate means, the sai.d at least one driving FET being connected between a logical output terminal of the second logic gate means and one power-source terminal, and having its gate terminal connected to receive the logical output signal of the first logic gate means, the load FET's being connected between the logical output terminal of the second logic gate means and another power-source terminal, and having their gate terminals connected with corresponding logical input terminals of the first logic gate means.
Claim 2
Dependent Claim
159 words
A logic circuit comprising: first logic gate means, comprising at least one logic gate circuit having a plurality of logical input terminals, and second logic gate means, comprising at least one logic gate circuit to which a logical output signal of the first logic gate means is applied, the second logic gate means having at least one driving field-effect transistor (FET), and load FET's at least equal in number to the logical input terminals of the first logic gate means, the sai.d at least one driving FET being connected between a logical output terminal of the second logic gate means and one power-source terminal, and having its gate terminal connected to receive the logical output signal of the first logic gate means, the load FET's being connected between the logical output terminal of the second logic gate means and another power-source terminal, and having their gate terminals connected with corresponding logical input terminals of the first logic gate means.
Claim 3
Dependent Claim
52 words
A logic circuit according to claim 1, wherein the first logic gate means is a multi-input NOR gate circuit, and the load FET's of the second logic gate means are connected in parallel with each other between the logical output terminal of the second logic gate means and the other power-source terminal.
Claim 4
Dependent Claim
26 words
A logic circuit as claimed in claim 2, wherein the inputs of the multi-input NOR gate are connected td the gates of corresponding load FET's. a
Claim 5
Dependent Claim
61 words
A logic circuit as claimed in claim 2, wherein each input of the multi-input NOR gate is connected to the gates of the FET's of a respective pair of load FET's of the second logic gate means, each such pair of load FET's comprising an enhancement-mode FET and a depletion-mode FET whose sources, drains and gates are respectively connected in common.
Claim 6
Dependent Claim
52 words
A logic circuit as claimed in claim 1, wherein the first logic gate means is a multi-input NAND gate circuit, and load FET's of the second logic gate means are connected in series with one another between the logical output terminal of the second logic gate and the other power source terminal.
Claim 7
Dependent Claim
26 words
A logic circuit as claimed in claim 5, wherein the inputs of the multi-input NAND gate circuit are connected to the gates of corresponding load FET's.
Claim 8
Dependent Claim
62 words
A logic circuit as claimed in claim 5, wherein each input of the multi-input NAND gate circuit is connected to the gates of the FET's of a respective pair of load FET's of the second logic gate means, each such pair of load FET's comprising an enhancement-mode FET and a depletion-mode FET whose sources, drains and gates are respectively connected in common.
Claim 9
Dependent Claim
118 words
A logic circuit as claimed in claim 1, . wherein the first logic gate means comprises a plurality of multi-input NOR gate circuits, and the second logic gate means comprises a plurality of groups of load FET's, the load FET's within each group being connected in parallel, the respective groups being provided in correspondence with respective NOR gate circuits, and the respective groups being connected in series with one another.between the logical output terminal of the second logic gate means and the other power source terminal, and a plurality of driving FET's, corresponding respectively to respective NOR gates, connected in parallel between the logical output terminal of the second logic gate means and the one power source terminal.
Claim 10
Dependent Claim
120 words
A logic circuit as claimed in claim 1, wherein the first logic gate means comprises a multi-input NOR gate circuit and a multi-input NAND gate circuit, and the second logic gate means comprises a parallel-connected group of load FET's and a serial -connected group of load FET's, inputs of the NOR gate circuit being connected respectively to gates of corresponding FET's of the parallel-connected group, inputs of the NAND gate circuit being connected respectively to gates of corresponding FET's of the serial-connected group, the parallel-connected group being connected in series with the serial-connected,group, and driving FET's, whose inputs are respectively connected to the outputs of the NAND gate circuit and the NOR gate circuit, connected in parallel with one another.
Claim 11
Dependent Claim
112 words
A logic circuit as claimed in claim 1, wherein the first logic gate means comprises a NOR gate circuit and a NAND gate circuit, and the second logic gate means comprises a parallel-connected group of load FET's and a serial-connected group of FET's, inputs of the NOR gate circuit being connected respectively to gates of corresponding FET's of the parallel-connected group, inputs of the NAND gate being connected respectively to gates of corresponding FET's of the serial-connected group, the serial-connected group being connected in parallel with the parallel-connected group,and driving FET's, whose inputs are respectively connected to the outputs of the NOR and NAND gate circuits, connected in series with one another.
Claim 12
Dependent Claim
92 words
A logic circuit as claimed in claim 1, wherein the first logic gate means comprises a plurality of NAND gate circuits, and the second logic gate means comprises a plurality of groups of load FET's, the load FET's within each group being connected in series, the respective groups being provided in correspondence with respective NAND gate circuits, and the respective groups being connected in parallel with one another, and a plurality of driving FET's, whose inputs are respectively connected to the outputs of said NAND circuits connected in series with one another.
Claim 13
Dependent Claim
113 words
A logic circuit having a plurality of logic gate circuits, at least one of those logic gate circuits comprising driving field-effect transistor (FET) means and load FET means connected in series between voltage supply terminals of the logic circuit, a signal output end of another of the logic gate circuits being connected to an input terminal of the driving FET means of the one logic gate circuit, and a circuit signal input end of that other logic gate/being connected to an input terminal of the load FET means, characterised in that the load FET means comprises an enhancement-mode FET and a depletion-mode FET whose sources, drains and gates are respectively connected in common.
Claim 14
Dependent Claim
113 words
A logic circuit having a plurality of logic gate circuits, at least one of those logic gate circuits comprising driving field-effect transistor (FET) means and load FET means connected in series between voltage supply terminals of the logic circuit, a signal output end of another of the logic gate circuits being connected to an input terminal of the driving FET means of the one logic gate circuit, and a circuit signal input end of that other logic gate/being connected to an input terminal of the load FET means, characterised in that the load FET means comprises an enhancement-mode FET and a depletion-mode FET whose sources, drains and gates are respectively connected in common.
Claim 15
Dependent Claim
18 words
A logic circuit as claimed in claim 12, wherein the said other logic gate circuit is an inverter.
Claim 16
Dependent Claim
65 words
A logic circuit as claimed in claim 12 or 13, wherein the said other logic gate circuit comprises a plurality of inverters, and the one logic gate circuit comprises a plurality of such load FET means, serially-connected, with their inputs respectively connected to inputs of the inverters, and the driving FET means comprises parallel-connected FET's whose inputs are respectively connected to outputs of the inverters.
Claim 17
Dependent Claim
65 words
A logic circuit as claimed in claim 12 or 13, wherein the said other logic gate circuit comprises a plurality of inverters, and the one logic gate circuit comprises a plurality of such load FET means, parallel-connected, with their inputs respectively connected to inputs of the inverters, and the driving FET means comprises serial-connected FET's whose inputs are respectively connected to outputs of the inverters.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.