EP0055553A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Information processor with initial programme loading
Assignee: Fujitsu Ltd
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Filing: 1981-12-17
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Granted: —
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Expires: 2001-12-17
Abstract
Abstract An information processor has a ROM memory exclusively storing a plurality of initial program loader (IPL) programs. The ROM memory has address inputs (A c or A 10 ) divided into two parts. One part (A o to A 8 ) is connected to a central processing unit (CPU) address bus for accessing contents within a selected IPL. The other part (Ag and A 10 ) is connected to IPL setting means which are operable to select a desired IPL. The IPL setting means comprises switches connected to address inputs (A 9 and A, o ) of the ROM.
Inventors
- 👤 Shosuke Mori
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 02:37
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/44; G06F9/4401; G06F9/4406; G06F9/441
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
137 words
An information processor having a plurality of initial program loader (IPL) programs, for execution by a central processing unit (CPU) of the processor when operation of the CPU is initiated, and operable respectively for loading desired execution programs into a first memory, comprising: a second memory which stores the plurality of IPL programs therein, some address terminals of the second memory being connected to the central processing unit through an address bus, the central processing unit being operable to set address bits corresponding to the said some address terminals, and an IPL setting part for selecting a desired one of the said plurality of IPL programs, remaining address terminals of the second memory being connected to the IPL setting part, the IPL setting part being operable to set address bits corresponding to the said remaining address terminals.
Claim 2
Dependent Claim
137 words
An information processor having a plurality of initial program loader (IPL) programs, for execution by a central processing unit (CPU) of the processor when operation of the CPU is initiated, and operable respectively for loading desired execution programs into a first memory, comprising: a second memory which stores the plurality of IPL programs therein, some address terminals of the second memory being connected to the central processing unit through an address bus, the central processing unit being operable to set address bits corresponding to the said some address terminals, and an IPL setting part for selecting a desired one of the said plurality of IPL programs, remaining address terminals of the second memory being connected to the IPL setting part, the IPL setting part being operable to set address bits corresponding to the said remaining address terminals.
Claim 3
Dependent Claim
40 words
An information processor as claimed in claim 1, wherein the said IPL setting part includes a plurality of switches which are connected to upper address bit input terminals of a ROM constituting the second memory in one-to- one correspondence thereto.
Claim 4
Dependent Claim
39 words
An information processor as claimed in claim 2, wherein the number of the said switches, and the number of the said upper address bit input terminals. corresponds to the number of peripheral equipments subject to control by the processor.
Claim 5
Dependent Claim
17 words
An information processor as claimed in claim 3, wherein the IPL programs correspond to respective peripheral equipments.
Claim 6
Dependent Claim
48 words
An information processor as claimed in claim 3 or 4, wherein communication between the CPU and a peripheral equipment is established by way of a common memory, through which command signals, status signals, error status signals and data signals are passed between the CPU and the peripheral equipment.
Claim 7
Dependent Claim
59 words
An information processor as claimed in claim 5, wherein the common memory has a status area and an error status area holding status and error status information corresponding to various situations that can arise in the peripheral equipment, an address of the common memory appropriate to a particular situation being accessed from the peripheral equipment when that situation arises.
Claim 8
Dependent Claim
24 words
An information processor as claimed in any one of claims 3 to 6, wherein a speech synthesis system is provided as a peripheral equipment.
Claim 9
Dependent Claim
23 words
An information processor as claimed in claim 7, wherein the speech synthesis system includes a magnetic bubble memory for storage of speech parameters.
Claim 10
Dependent Claim
21 words
An information processor as claimed in claim 8, wherein the magnetic bubble memory is provided in the form of a cassette.
References Cited (Backward Citations)
No citation records indexed.
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