EP0055339A2
Expired / Lapsed
EP
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Memory system comprising dynamic memory cells
Assignee: International Business Machines Corp
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Filing: 1981-10-09
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Granted: —
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Expires: 2001-10-09
Abstract
Abstract Memory system comprising dynamic memory cells, wherein each cell comprises a switchable cell device (10) and a capacitive node (12), wherein said switchable cell device [10) is connected to a bit line (14) to read the charge stored at said (12) node and to a first word line (16) to selectively switch said cell device (10) responsive to a first signal in said word line (16).Means are provided for rewriting the cell after reading without discharging the bit line to thereby improve cycle time. The cell includes an independently operated device (24) to access the capacitive storage node (12) to discharge the node of any charge thereon after the reading of a low or no charge bit on the capacitive storage node.
Inventors
- 👤 Endre Philip Thoma
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 04:49
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4094
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
190 words
Memory system comprising dynamic memory cells, wherein each cell comprises a switchable cell device (10) and a capacitive node (12), wherein said switchable cell device (10) is connected to a bit line (14) to read the charge stored at said (12) node and to a first word line (16) to selectively switch said cell device (10) responsive to a first signal in said word line (16), and wherein the system includes a sense amplifier (20) to sense the read charge on said bit line (14), characterized by a cell write device (24) being connected to a write line (26) and to said storage node (12) and also connected to a second word line (30) to selectively switch said cell write device (24) responsive to a second signal in said second word line (30), and means to selectively connect said write (26) line to a low voltage value responsive to a sensed low charge at said capacitive node (12), whereby a sensed low charge in said cell is rewritten independently of said bit line (14) and a high charge in said cell is rewritten by said bit line (14) upon reading.
Claim 2
Dependent Claim
190 words
Memory system comprising dynamic memory cells, wherein each cell comprises a switchable cell device (10) and a capacitive node (12), wherein said switchable cell device (10) is connected to a bit line (14) to read the charge stored at said (12) node and to a first word line (16) to selectively switch said cell device (10) responsive to a first signal in said word line (16), and wherein the system includes a sense amplifier (20) to sense the read charge on said bit line (14), characterized by a cell write device (24) being connected to a write line (26) and to said storage node (12) and also connected to a second word line (30) to selectively switch said cell write device (24) responsive to a second signal in said second word line (30), and means to selectively connect said write (26) line to a low voltage value responsive to a sensed low charge at said capacitive node (12), whereby a sensed low charge in said cell is rewritten independently of said bit line (14) and a high charge in said cell is rewritten by said bit line (14) upon reading.
Claim 3
Dependent Claim
52 words
Memory system as claimed in claim 1, characterized in that said means to selectively connect said write line (26) to low voltage includes a second device (42) connected in series with said cell write device (24), and means to selectively turn both devices on at the same time to discharge said node.
Claim 4
Dependent Claim
25 words
Memory system as claimed in claim 2, characterized in that said second device (42) is operable by said sense amplifier (20) sensing a low voltage.
Claim 5
Dependent Claim
24 words
Memory system as claimed in claim 3, characterized in that said cell write device (42) is pulsed subsequently to a reading of a node.
Claim 6
Dependent Claim
34 words
Memory system as claimed in claim 1 to 4, characterized in that isolation means (18) are connected to isolate the sense amplifier (20) from said cell after the capacitive node charge has been sensed.
Claim 7
Dependent Claim
19 words
Memory system as claimed in claim 5, characterized in that said isolation means includes a series connected device (18).
Claim 8
Dependent Claim
36 words
Memory system as claimed in claim 6, characterized in that said series connected device (18) is normally on and means to switch said device off after the capacitive charge is sensed by said sense amplifier (20).
Claim 9
Dependent Claim
18 words
Memory system as claimed in claims 1 to 7, characterized in that said devices are field effect transistors.
References Cited (Backward Citations)
No citation records indexed.
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