EP0055182A2
Expired / Lapsed
EP
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High speed nonvolatile electrically erasable memory cell and system
Assignee: Fairchild Semiconductor Corp
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Filing: 1981-12-21
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Granted: —
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Expires: 2001-12-21
Abstract
Abstract A process forfabricating an electricallyerasablenonvo- latile memory cell comprises forming a first region of insulating material which is less than about 200 Angstroms thick on a selected surface portion of an electrically isolated relatively lithtly doped pocket of epitaxial silicon of a first conductivity type such that first and second surface areas of the epitaxial pocket are exposed. Regions of the epitaxial pocket underlying the first and second exposed surface areas are doped such that first and second relatively lightly doped epitaxial regions of a second conductivity type are formed in the epitaxial pocket. A first relatively heavily doped polysilicon region of the first conductivity type is formed on the first insulating region and a second relatively heavily doped polysilicon region of the first conductivity type is formed on the second relatively lightly doped epitaxial region. A second region of insulating material is formed over exposed surfaces of the first polysilicon region of the first conductivity type and a third region of insulating material is formed over exposed surfaces of the second polysilicon region of the first conductivity type such that first and second surface portions of the second relatively lightly doped epitaxial region are exposed. The regions of the epitaxial pocket underlying the surface of the first relatively lightly doped epitaxial region and the first and second surface portions of the second relatively lightly doped epitaxial region are doped such that first, second and third relatively heavily doped epitaxial regions of the second 'conductivity type are formed in the epitaxial pocket. A first relatively heavily doped polysilicon region of the second conductivity type is formed on the second insulating region and a second relatively heavily doped polysilicon region of the second conductivity type is formed on the third insulating region.
Inventors
- 👤 Andrew Tickle
- 👤 Madhukar B. Vora
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 00:25
CPC Classifications
H; H10; H10B; H10B41/00; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0433; H10B69/00
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
291 words
A process for fabricating an electrically erasable nonvolatile memory cell, characterized by the steps of: (a) forming a first region of insulating material, having a thickness which permits tunneling therethrough, on a selected surface portion of an electrically isolated, relatively lightly doped pocket of epitaxial silicon of a first conductivity type such that first and second surface areas of said epitaxial pocket are exposed; (b) doping regions of said epitaxial pocket underlying said first and second exposed surface areas such that first and second relatively lightly doped epitaxial regions of a second conductivity type are formed in said epitaxial pocket; (c) forming a first relatively heavily doped polysilicon region of said first conductivity type on said first insulating region and a second relatively heavily doped polysilicon region of said first conductivity type on said second relatively lightly doped epitaxial region; (d) forming a second region of insulating material over exposed surfaces of said first polysilicon region of said first conductivity type and a third region of insulating material over exposed surfaces of said second polysilicon region of said first conductivity type such that first and second surface portions of said second relatively lightly doped epitaxial region are exposed; (e) doping regions of said epitaxial pocket underlying the surface of said first relatively lightly doped epitaxial region and said first and second surface portions of said second relatively lightly doped epitaxial region such that first, second and third relatively heavily doped epitaxial regions of said second conductivity type are formed in said epitaxial pocket; and (f) forming a first relatively heavily doped polysilicon region of said second conductivity type on said second insulating region and a second relatively heavily doped polysilicon region of said second conductivity type on said third insulating region.
Claim 2
Dependent Claim
291 words
A process for fabricating an electrically erasable nonvolatile memory cell, characterized by the steps of: (a) forming a first region of insulating material, having a thickness which permits tunneling therethrough, on a selected surface portion of an electrically isolated, relatively lightly doped pocket of epitaxial silicon of a first conductivity type such that first and second surface areas of said epitaxial pocket are exposed; (b) doping regions of said epitaxial pocket underlying said first and second exposed surface areas such that first and second relatively lightly doped epitaxial regions of a second conductivity type are formed in said epitaxial pocket; (c) forming a first relatively heavily doped polysilicon region of said first conductivity type on said first insulating region and a second relatively heavily doped polysilicon region of said first conductivity type on said second relatively lightly doped epitaxial region; (d) forming a second region of insulating material over exposed surfaces of said first polysilicon region of said first conductivity type and a third region of insulating material over exposed surfaces of said second polysilicon region of said first conductivity type such that first and second surface portions of said second relatively lightly doped epitaxial region are exposed; (e) doping regions of said epitaxial pocket underlying the surface of said first relatively lightly doped epitaxial region and said first and second surface portions of said second relatively lightly doped epitaxial region such that first, second and third relatively heavily doped epitaxial regions of said second conductivity type are formed in said epitaxial pocket; and (f) forming a first relatively heavily doped polysilicon region of said second conductivity type on said second insulating region and a second relatively heavily doped polysilicon region of said second conductivity type on said third insulating region.
Claim 3
Dependent Claim
16 words
A process according to claim 1 characterized in that said first conductivity type is N type.
Claim 4
Dependent Claim
18 words
A process according to claim 1 or 2 characterized in that said second conductivity type is P type.
Claim 5
Dependent Claim
18 words
A process according to claim 1, 2 or 3 characterized in that said insulating material is silicon dioxide.
Claim 6
Dependent Claim
19 words
A process according to any one of the previous claims, characterized in that said doping is by ion implantation.
Claim 7
Dependent Claim
72 words
A process according to any one of the previous claims, characterized in that said first relatively heavily doped polysilicon region of said second conductivity type is electrically isolated from said epitaxial pocket and said second heavily doped polysilicon region of said second conductivity type such that said second relatively heavily doped region of said second conductivity type contacts said second and third relatively heavily doped epitaxial regions of said second conductivity type.
Claim 8
Dependent Claim
109 words
A process according to any one of the previous claims, characterized in that step (a) is preceded by the steps of: forming a relatively heavily doped buried layer region of said first conductivity type in the upper surface of a second conductivity type substrate; forming a relatively lightly doped epitaxial silicon layer of a first conductivity type on the surface of said buried layer region and said substrate; and forming a closed loop of said isolation oxide which extends through said epitaxial layer to the junction between said buried layer region and said substrate to form an electrically isolated relatively lightly doped epitaxial pocket of said first conductivity type.
Claim 9
Independent Claim
351 words
A method for encoding binary data into an electrically erasable memory, said memory comprising a matrix of memory cells formed as a plurality of rows and a plurality of columns of said cells each of said cells comprising a floating gate field effect pMOS transistor for storage of binary data and an npn bipolar transistor for selective access to stored data, a plurality of X write lines the control gate of each said storage transistor in a row of said memory cells being connected to an X write line corresponding to said row, a plurality of X sense lines the emitter of each said bipolar transistor in a row of said memory cells being connected to an X sense line corresponding to said row, a plurality of source lines the source of each said bipolar transistor in a row of said memory cells being connected to a source line corresponding to said row, and a plurality of Y sense lines the collector of each said bipolar transistor in a column of said memory cells being connected to a Y sense line corresponding to said column, the method characterized by the steps of: (a) applying an erase voltage to each of said Y sense lines and, simultaneously, maintaining each of said X sense lines at said erase voltage, maintaining each of said X write lines at ground and applying said erase voltage to each of said source lines such that each of said storage transistors assumes a relatively negative threshold state; and (b) applying a write voltage to selected X write lines while maintaining unselected X write lines at ground, and, simultaneously, maintaining selected Y sense lines at ground and unselected Y sense lines at an inhibit voltage which is less than said write voltage and maintaining each of said X sense lines at an intermediate voltage which is equal to or less than the base/emitter breakdown voltage of said bipolar transistors such that the storage transistors of memory cells located at the intersections of said selected X write lines and said selected Y sense lines assume a relatively positive threshold state.
Claim 10
Independent Claim
351 words
A method for encoding binary data into an electrically erasable memory, said memory comprising a matrix of memory cells formed as a plurality of rows and a plurality of columns of said cells each of said cells comprising a floating gate field effect pMOS transistor for storage of binary data and an npn bipolar transistor for selective access to stored data, a plurality of X write lines the control gate of each said storage transistor in a row of said memory cells being connected to an X write line corresponding to said row, a plurality of X sense lines the emitter of each said bipolar transistor in a row of said memory cells being connected to an X sense line corresponding to said row, a plurality of source lines the source of each said bipolar transistor in a row of said memory cells being connected to a source line corresponding to said row, and a plurality of Y sense lines the collector of each said bipolar transistor in a column of said memory cells being connected to a Y sense line corresponding to said column, the method characterized by the steps of: (a) applying an erase voltage to each of said Y sense lines and, simultaneously, maintaining each of said X sense lines at said erase voltage, maintaining each of said X write lines at ground and applying said erase voltage to each of said source lines such that each of said storage transistors assumes a relatively negative threshold state; and (b) applying a write voltage to selected X write lines while maintaining unselected X write lines at ground, and, simultaneously, maintaining selected Y sense lines at ground and unselected Y sense lines at an inhibit voltage which is less than said write voltage and maintaining each of said X sense lines at an intermediate voltage which is equal to or less than the base/emitter breakdown voltage of said bipolar transistors such that the storage transistors of memory cells located at the intersections of said selected X write lines and said selected Y sense lines assume a relatively positive threshold state.
Claim 11
Dependent Claim
16 words
A method according to claim 8 characterized in that said erase voltage is about +20 volts.
Claim 12
Dependent Claim
18 words
A method according to claim 8 or 9 characterized in that said write voltage is about +20 volts.
Claim 13
Dependent Claim
19 words
A method according to claim 8, 9 or 10 characterized in that said inhibit voltage is about +10 volts.
Claim 14
Independent Claim
20 words
A method according to any one of the previous claims characterized in that said intermediate voltage is about +5 volts.
Claim 15
Dependent Claim
110 words
A method according to claim 8 or 12 characterized by the further steps of: (a) maintaining a selected X sense line of a row of memory cells at ground and, simultaneously, maintaining unselected X sense lines and each of said Y sense lines at a read voltage such that memory cells connected to said selected X sense line and having storage transistors in said low threshold state are relatively less conducting and memory cells connected to said selected X sense line and having storage transistors in said high threshold state are relatively more conducting; and (b) monitoring the relative conductance of memory cells connected to said selected X sense lines.
Claim 16
Dependent Claim
16 words
A method according to claim 13 characterized in that said read voltage is about +3 volts.
References Cited (Backward Citations)
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