EP0055129A2
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1981-12-22
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Granted: —
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Expires: 2001-12-22
Abstract
Abstract A semiconductor memory device includes a plurality of memory blocks (1-1,1-2,1-3,1-4) each comprising memory cells arranged in rows and columns, a plurality of pairs of data buses (DB 1 , DB 1 ; ... DB 4 , DB 4 ) connected respectively to the said memory blocks, cell selection means (2,3, 4, 5) for selecting one memory cell in each memory block so as to place the selected memory cells in simultaneous connection with the respective data buses, and write circuitry (6, 7) for writing preselected input data into each of the selected memory cells. The device is provided with a read test circuit (10) operable, on the basis of a set of signals received respectively by way of all the said pairs of data buses simultaneously, to provide a fault-indicating response if the said set of signals differs from a predetermined desired set appropriate to desired normal operation of the device. Such testing of one memory cell from each memory block simultaneously can serve to reduce the time needed to test the memory device as a whole.
Inventors
- 👤 Takeo Tatematsu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 16:23
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/34
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
152 words
A semiconductor memory device comprising: first and second power supply terminals; a plurality of memory blocks each comprising memory cells arranged in rows and columns; a plurality of pairs of data buses each pair being connected to one of said memory blocks; a cell selection means for selecting one memory cell within each of said memory blocks so as to connect the selected memory cells to the corresponding data buses; a block selection circuit for selecting one pair of said pairs of data buses during the write mode so as to write input data into one of the selected memory cells; and a read test circuit, connected to said first and second power supply terminals and to said data buses, for detecting the potential of each of said data buses so as to check simultaneously whether or not the data at said data buses transmitted from the selected memory cells is correct.
Claim 2
Dependent Claim
152 words
A semiconductor memory device comprising: first and second power supply terminals; a plurality of memory blocks each comprising memory cells arranged in rows and columns; a plurality of pairs of data buses each pair being connected to one of said memory blocks; a cell selection means for selecting one memory cell within each of said memory blocks so as to connect the selected memory cells to the corresponding data buses; a block selection circuit for selecting one pair of said pairs of data buses during the write mode so as to write input data into one of the selected memory cells; and a read test circuit, connected to said first and second power supply terminals and to said data buses, for detecting the potential of each of said data buses so as to check simultaneously whether or not the data at said data buses transmitted from the selected memory cells is correct.
Claim 3
Dependent Claim
165 words
A device as set forth in claim 1, wherein said read test circuit comprises: an output terminal; a plurality of first transistors each having a drain connected to said first power supply terminal, a gate connected to one positive data bus of said data buses and a source connected to said output terminal; a plurality of second transistors each having a drain connected to said output terminal, a gate connected to one negative data bus of said data buses and a source; and a third transistor having a drain connected to the sources of said second transistors, a gate and a source connected to said second power supply terminal, the potential of the gate of said third transistor being set,up at a level so as to be in a non-conductive state when said third transistor is in the normal mode and being set up at a level so as to be in a conductive state when said third transistor is in the read test mode.
Claim 4
Dependent Claim
30 words
A device as set forth in claim 2, wherein said read test circuit comprises a plurality of resistors each connected in series to one of said first and second transistors.
Claim 5
Dependent Claim
114 words
A device as set forth in claim 1, wherein said read test circuit comprises: first and second resistors connected to said second power supply terminal; first and second output terminals each connected to said first and second resistors, respectively; a plurality of fourth transistors connected in series between said first output terminal and said first power supply terminal, each of said fourth transistors having a gate connected to one positive data bus of said data buses; and a plurality of fifth transistors connected in series between said second output terminal and said first power supply terminal, each of said fifth transistors having a gate connected to one negative data bus of said data buses.
Claim 6
Dependent Claim
63 words
A device as set forth in claim 1, wherein said block selection circuit comprises: a plurality of pairs of transfer gate transistors, each pair connected to one of said pairs of data buses, for receiving input data; and a plurality of decoders, each connected to one of said pairs of transfer gate transistors, for selecting one pair of said pairs of data buses.
Claim 7
Dependent Claim
57 words
A device as set forth in claim 5, wherein said block selection circuit further comprises a simultaneous--write means, connected to each of said decoders, for enabling said decoders to select all of said pairs of data buses so as to simultaneously write input data into all of the selected memory cells selected by said cell selection means.
Claim 8
Dependent Claim
146 words
A semiconductor memory device including: a plurality of memory blocks (1-1,....1-4) each comprising memory cells arranged in rows and columns; a plurality of pairs of data buses (DB 1' DB 1 ;... DB 4 ,DB 4 )which pairs are connected respectively to the said memory blocks; cell selection means (2,3,4,5) for selecting one memory cell within each of said memory blocks so as to place the selected memory cells in simultaneous connection with the respective corresponding data buses; write circuitry (6,7) for writing preselected input data into each of the selected memory cells; and a read test circuit (10) operable on the basis of a set of signals received respectively by way of all the said pairs of data buses simultaneously to provide a fault-indicating response if the said set of signals differs from a predetermined desired set appropriate to desired normal operation of the device.
Claim 9
Dependent Claim
146 words
A semiconductor memory device including: a plurality of memory blocks (1-1,....1-4) each comprising memory cells arranged in rows and columns; a plurality of pairs of data buses (DB 1' DB 1 ;... DB 4 ,DB 4 )which pairs are connected respectively to the said memory blocks; cell selection means (2,3,4,5) for selecting one memory cell within each of said memory blocks so as to place the selected memory cells in simultaneous connection with the respective corresponding data buses; write circuitry (6,7) for writing preselected input data into each of the selected memory cells; and a read test circuit (10) operable on the basis of a set of signals received respectively by way of all the said pairs of data buses simultaneously to provide a fault-indicating response if the said set of signals differs from a predetermined desired set appropriate to desired normal operation of the device.
References Cited (Backward Citations)
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