EP0054853A2
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1981-12-11
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Granted: —
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Expires: 2001-12-11
Abstract
Abstract A semiconductor memory device comprising a circuit (DIS) which flows a discharge current to a selected word line (W,-, ... W n -), wherein a circuit (Z 1' ... , Z n ) for detecting change of decoder input is provided, and thereby said discharge current temporarily flows only when said selected word lines shift to the non-selected condition.
Inventors
- 👤 Yasuhisa Sugo
- 👤 Kazuhiro Toyoda
- 👤 Katuyuki Yamada
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 15:39
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/415
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
126 words
A semiconductor memory device comprising the discharge current circuit (DIS) which provides the first transistor and gives a discharge current to a word line (W 1 - ,... W n - ) via said first transistor (T 2 ), characterised in that said semiconductor memory device comprises a detection circuit (Z 1 ,....Z n ) which detects change of address signal and a second transistor (T 3 ) which forms a current switch together with said first transistor and turns OFF in accordance with a detected output of said detection circuit (Z 1 ,....Z n ), whereby discharge current flows temporarily through said word line (W i - ) only when said first transistor (T 2 ) turns ON due to the change of address signal.
Claim 2
Dependent Claim
126 words
A semiconductor memory device comprising the discharge current circuit (DIS) which provides the first transistor and gives a discharge current to a word line (W 1 - ,... W n - ) via said first transistor (T 2 ), characterised in that said semiconductor memory device comprises a detection circuit (Z 1 ,....Z n ) which detects change of address signal and a second transistor (T 3 ) which forms a current switch together with said first transistor and turns OFF in accordance with a detected output of said detection circuit (Z 1 ,....Z n ), whereby discharge current flows temporarily through said word line (W i - ) only when said first transistor (T 2 ) turns ON due to the change of address signal.
Claim 3
Dependent Claim
35 words
A semiconductor memory device as set forth in claim 1, wherein the waveform shaping means (DLY) is connected between said detecting circuit (Z 1 ,..., Z n ) and said second transistor (T 3 ).
Claim 4
Dependent Claim
89 words
A semiconductor memory device as set forth in claim 1, wherein said detecting circuit (Z l ,...,Z n ) comprises a third transistor which receives a first address signal at the base, a forth transistor which receives a second address signalwhich is complementary to the first address signal at the base and a fifth transistor to the base of which the first reference volage is applied, and the emitters of said third, fourth and fifth transistors (T 4 , T 5 , T 6 ) are connected in common.
Claim 5
Dependent Claim
57 words
A semiconductor memory device as set forth in claim 3, wherein said first reference voltage is higher than the voltage at which said first address signal and said second address signal become the same in the level when the high level and low level of said both signals are mutually inverted but lower than said high level.
Claim 6
Dependent Claim
45 words
A semiconductor memory device as set forth in claim 2, wherein said waveform shaping means (DLY) comprises a means for delaying an input signal of said waveform shaping means and a means for obtaining logical OR circuit of said input signal and said delayed signal.
References Cited (Backward Citations)
No citation records indexed.
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