Semiconductor memory device

Claim 2

A semiconductor memory device characterized by comprising: a memory cell which has a semiconductor region of first conductivity type having an impurity region of second conductivity type, a first conductive layer formed on said semiconductor region with a first insulating film interposed therebetween, a second conductive layer which is formed on said semiconductor region with a second insulating film interposed therebetween and which has a function of storing data, and a third conductive layer which is formed on said second conductive layer with a third insulating film interposed therebetween and which is electrically insulated from said first and second conductive layers; and means for discharging an electron from said second conductive layer by field emission which includes first means for applying a voltage of high level for erasing data to said first conductive layer to erase the data, and second means for applying a voltage of low level to said third conductive layer to erase the data.

Claim 3

A semiconductor memory device according to claim 1, characterized in that a relation CFC > 2C FB is established between a capacitance C FC between said second conductive layer and said third conductive layer and a capacitance C FB between said second conductive layer and said semiconductor region.

Claim 4

A semiconductor memory device according to claim 1 or 2, characterized in that a relation C FC + C FB > 5CFE is established between the capacitance C FC between said second conductive.layer and said third conductive layer, the capacitance C FB between said second conductive layer and said semiconductor region, and a capacitance C FE between said second conductive -. layer and said first conductive layer.

Claim 5

A semiconductor memory device according to claim 1, characterized in that said second conductive layer and said third conductive layer are formed on a substrate region of said semiconductor region in which a channel is formed, said second conductive layer has a width smaller than a channel length, and said third conductive layer has a width equal to or greater than the channel length.

Claim 6

'A semiconductor memory device according to claim 1 or 4, characterized in that a plurality of said memory cells are formed in .a memory matrix so that said first conductive layers of the memory cells of each column are commonly connected by an erase line, said impurity regions of the memory cells of each column are commonly connected by a column line, and said third conductive layers of each row are commonly connected by a row line; and said first means is arranged in each erase line of said memory matrix, whereby data may be erased in each column of said memory matrix.

Claim 7

A semiconductor memory device according to claim 5, characterized in that said first means comprises: a plurality of switching means each connected to each of said erase lines; and voltage supplying means for supplying a voltage of high level to said switching means in order to apply a voltage of high level for erasing the data to said erase line.

Claim 8

A semiconductor memory device according to claim 6, characterized in that each of said switching means comprises: a MOS transistor; and switching signal supply means connected to a gate of said MOS transistor.

Claim 9

A semiconductor memory device according to claim 7, characterized in that said switching signal supply means is a decoder.

Claim 10

A semiconductor memory device according to claim 6, characterized in that each of said switching means comprises: a first MOS transistor one end of which is connected to said erase line and the other end of which is grounded, an inverter an output end of which is connected to a gate of said first MOS transistor, a column decoder connected to an input end of said inverter, a second MOS transistor which is arranged between the output end of said column decoder and said column line, a voltage of low level being applied to a gate of said second MOS transistor when the data is erased and a voltage of high level being applied to the gate of said second MOS transistor when the data is read out or written; and said voltage supplying means further comprises: a resistor connected in series to one end of said first MOS transistor.

Claim 11

A semiconductor memory device according to claim 6, characterized in that said each switching means comprises: a first MOS transistor one end of which is connected to said erase line and the other end of which is connected said voltage supplying means; boost means an output end of which is connected to a gate of said first MOS transistor; a column decoder connected to an input end of said boost means; and a second MOS transistor arranged between output end of said column decoder and column line, a voltage of low level being applied to a gate of said second M OS transistor when the data is erased and a voltage of high level being applied to the gate of said second MOS transistor when the data is written or read out.

Claim 12

A semiconductor memory device according to claim 5, characterized in that said second means is provided in each of said row lines, whereby data may be erased for each bit unit.

Claim 13

A semiconductor memory device according to claim 11, characterized in that said second means sets a potential of a.selected row line at high level when the data is read out or written; and said second means sets the potential of the selected row line at low level when the data is erased and potential of nonselected row lines at high level when the data is erased.

Claim 14

A semiconductor memory device according to claim 12, characterized in that said first means comprises: first switching means connected to each erase line; and voltage supplying means for supplying a voltage of high level to said first switching means in order to apply a voltage of high level to said erase line when the data is erased.

Claim 15

A semiconductor memory device according to claim 13, characterized in that said first switching means comprises: a first MOS transistor one end of which is connected to each of said erase lines and the other end of which is grouned, an inverter an output end of which is connected to a gate of said first MOS transistor, a column decoder connected to an input end of said inverter, and a second MOS transistor arranged between each output end of said column decoder and each column line, a voltage of low level being supplied to a gate of said second MOS transistor when the data is erased and a voltage of high level being supplied to the gate of the second MOS transistor when the data is read out or written; and said voltage supplying means further comprises: a resistor connected in series to one end of said first MOS transistor.

Claim 16

A semiconductor memory device according to claim 14, characterized in that said second means comprises: a third MOS transistor one end of which is connected to each row line, a first control signal being supplied to a gate of said third MOS transistor which goes low level when the data is erased and which goes high level when the data is read out or written; a fourth MOS transistor one end of which is connected to each row line, a second control signal which has an inverted relation with the first control signal being supplied to a gate of said fourth MOS transistor; a fifth MOS transistor connected to-the other end of said fourth MOS transistor, the other end of said fifth MOS transistor being grounded and a voltage of high level which is equal to the voltage of high level for erasing the data being supplied to one end of said fifth MOS transistor through a resistor; and a row decoder connected to the other end of said third MOS transistor and a gate of said fifth MOS transistor.

Claim 17

A semiconductor memory device according to claim 14, characterized in that said second means comprises: a third MOS transistor one end of which is connected to each row line, a first control signal being supplied to a gate of said third MOS transistor which goes low level when the data is erased and which goes high level when the data is read out or written; a fourth MOS transistor one end of which is connected to said row line; a fifth MOS transistor connected to the other end of said fourth MOS transistor, the other end of said fifth MOS transistor being grounded and a second control signal which has an inverted relation with said first control signal being supplied to a gate of said fifth MOS transistor; voltage supply means for supplying a voltage which has the same level as the voltage of high level for erasing the data to one end of said fourth MOS transistor through a resistor; and a row decoder connected to the other end of said third MOS transistor and the gate of said fifth MOS transistor.

Claim 18

A semiconductor memory device according to claim 14, characterized in that said second means comprises: a third MOS transistor one end of which is connected to each row line, a first control signal being supplied to a gate of said third MOS transistor which goes low level when the data is erased and which goes high level when the data is written or read out; a fourth MOS transistor one end of which is connected to said row line, a second control signal which has an inverted relation with said first control signal being supplied to a gate of said fourth MOS transistor; and boost means to which is input a voltage equal to the voltage of high level for erasing the data and which boosts the input voltage to supply to the other end of said fourth MOS transistor.

Claim 19

A semiconductor memory device according to claim 17, characterized in that said boost means comprises: a fifth MOS transistor which receives at one end thereof a voltage equal to the voltage of high level for erasing the data, said second control signal being supplied to the gate of said fifth MOS transistor; a sixth MOS transistor one end of which is connected to the other end of said fifth MOS transistor and the other end of which is connected to the other end of said fourth MOS transistor; a seventh MOS transistor one end of which is connected to the other end of said sixth MOS transistor, the other end of which is grounded and a gate of which is connected to an output end of a row decoder; an eighth MOS transistor one end of which is connected to one end of said fifth MOS transistor, the other end of which is connected to a gate of said sixth MOS transistor and a gate of which is connected to one end of said fifth MOS transistor; and a capacitor connected to the gate of the sixth MOS transistor and to a node of said sixth and seventh MOS transistors.

Claim 20

A semiconductor memory device according to claim 13, characterized in that said each switching means comprises: a first MOS transistor one end of which is connected to said erase line and the other end of which is connected said voltage supplying means; a first boost means an output end of which is connected to a gate of said first MOS transistor; a column decoder connected to an input end of said first boost means; and a second MOS transistor arranged between output end of said column decoder and column line, a voltage of low level being applied to a gate of said second MOS transistor when the data is erased and a voltage of high level being applied to the gate of said second MOS transistor when the data is written or read out.

Claim 21

A semiconductor memory device according to claim 19, characterized in that said second means comprises: a third MOS transistor one end of which is connected to each row line, a first control signal being supplied to a gate of said third MOS transistor which goes low level when the data is erased and which goes high level when the data is read out or written; a fourth MOS transistor one end of which is connected to each row line, a second control signal which has an inverted relation with the first control signal being supplied to a gate of said fourth MOS transistor; a fifth MOS-transistor connected to the other end of said fourth MOS transistor, the other end of said fifth MOS transistor being grounded and a voltage of high level which is equal to the voltage of high level for erasing the data being supplied to one end of said fifth MOS transistor through a resistor; and a row decoder connected to the other end of said third MOS transistor and a gate of said fifth MOS transistor.

Claim 22

A semiconductor memory device according to claim 19, characterized in that said second means comprises: a third MOS transistor one end of which is connected to each row line, a first control signal being supplied to a gate of said third MOS transistor which goes low level when the data is erased and which goes high level when the data is read out or written; a fourth MOS transistor one end of which is connected to said row line; a fifth MOS transistor connected to the other end of said fourth MOS transistor, the other end of said fifth MOS transistor being grounded and a second control signal which has an inverted relation with said first control signal being supplied to a gate of said fifth MOS transistor; voltage supply means for supplying a voltage which has the same level as the voltage of high level for erasing the data to one end of said fourth MOS transistor through a resistor; and a row decoder connected to the other end of said third MOS transistor and the gate of said fifth MOS transistor.

Claim 23

A semiconductor memory device according to claim 19, characterized in that said second means comprises: a third MOS transistor one end of which is connected to each row line, a first control signal being supplied to a gate of said third MOS transistor which goes low level when the data is erased and which goes high level when the data is written or read out; a fourth MOS transistor one end of which is connected to said row line, a second control signal which has an inverted relation with said first control signal being supplied to a gate of said fourth MOS transistor; and a second boost means to which is input a voltage equal to the voltage of high level for erasing the data and which boosts the input voltage to supply to the other end of said fourth MOS transistor.

Claim 24

A semiconductor memory device according to claim 22, characterized in that said second boost means comprises: a fifth MOS transistor which receives at one end thereof a voltage equal to the voltage of high level for erasing the data, said second control signal being supplied to the gate of said fifth MOS transistor; a sixth MOS transistor one end of which is connected to the other end of said fifth MOS transistor and the other end of which is connected to the other end of said fourth MOS transistor; a seventh MOS transistor one end of which is connected to the other end of said sixth MOS transistor, the other end of which is grounded and a gate of which is connected to an output end of a row decoder; an eighth MOS transistor one end of which is connected to one end of said fifth MOS transistor, the other end of which is connected to a gate of said sixth MOS transistor and a gate of which is connected to one end of said fifth MOS transistor; and a capacitor connected to the gate of the sixth MOS transistor and to a node of said sixth and seventh MOS transistors.

Claim 25

A semiconductor memory device according to claim 1 or 4, characterized in that a plurality of said memory cells are arranged in a matrix form; and a third means is provided for supplying substantially the same voltage to said first conductive layers and said third conductive layers of said memory cells aligned on a selected row of said memory matrix when the data is read out or written.

Claim 26

A semiconductor memory device according to claim 24, characterized in that said first conductive layers of said memory cells in each row unit are commonly connected to a row line, and said third conductive layers of said memory cells in each row unit are commonly connected to an erase line; and said third means comprises: a first MOS transistor one end of which is connected to said erase line, the other end of which receives a voltage of high level for erasing the data and a gate of which receives a first control signal, said first MOS transistor being rendered conductive by said first control signal when the data is erased, and a second MOS transistor arranged between said erase line and said row line, a second control signal being supplied to a gate of said second MOS transistor in order to turn on said second MOS transistor when the data is read out or written.