EP0054322A1
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EP
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Phase sensitive detector
Assignee: Koninklijke Philips NV
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Filing: 1981-11-23
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Granted: —
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Expires: 2001-11-23
Abstract
Abstract detector comprising two D-type flip-flops (701) and (702) which are arranged so that in response to data pulses DP and clock pulses CK they produce respective pulse sequences 01 and D2. An exclusive OR gate (703) receives the pulse sequences 01 and D2. and an exclusive OR gate (704) receives the pulse sequence 01 and the data pulses DP. The clock pulses CK can be up to one half a clock pulse period late or up to one half a clock pulse period early relative to a desired phase relationship of the clock pulses CK with the data pulses DP. Accordingly, as the actual relative phase is correct, late or early, the duration of the logical output from the gate (704) will be the same as, relatively longer than or relatively shorter than the duration of the logical output from the gate (703). The two gate outputs control respective current sources (707) and (708) of a current source circuit (705) to feed current into an extract current from a capacitor (203). The voltage across the capacitor (203) serves as a control voltage for altering the phase of the clock pulses CK as produced by some form of oscillator to tend to bring it into the desired phase relationship with the data pulses DP.
Inventors
- 👤 Christopher Paul Summers
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 12:06
CPC Classifications
H; H03; H03D; H03D13/00; H03D13/003; H03D13/004; H04; H04L; H04L7/00; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
195 words
A phase sensitive detector for producing a control signal, which is indicative of phase discrepancy between data pulses of the NRZ type and clock pulses whose cycle period is equal to a data bit period and which can be used to correct the phase of the clock pulses to achieve a required phase relationship between the data pulses and the clock pulses, which phase sensitive detector comprises a first D-type flip-flop having a D input, a clock input and a logic output, and which phase sensitive detector is characterised in that said D input is connected to receive said data pulses and said clock input is connected to receive said clock pulses, that a second D-type flip-flop is provided which has its D input connected to the logic output of said first D-type flip-flop and its clock input connected to receive said clock pulses via an inverter, and that the logic outputs of said first and second D-type flip-flops are connected, respectively, to respective first inputs of first and second exclusive OR-gates, the outputs of which are connected to means for producing said control signal in accordance with the logic values at these gate outputs.
Claim 2
Dependent Claim
195 words
A phase sensitive detector for producing a control signal, which is indicative of phase discrepancy between data pulses of the NRZ type and clock pulses whose cycle period is equal to a data bit period and which can be used to correct the phase of the clock pulses to achieve a required phase relationship between the data pulses and the clock pulses, which phase sensitive detector comprises a first D-type flip-flop having a D input, a clock input and a logic output, and which phase sensitive detector is characterised in that said D input is connected to receive said data pulses and said clock input is connected to receive said clock pulses, that a second D-type flip-flop is provided which has its D input connected to the logic output of said first D-type flip-flop and its clock input connected to receive said clock pulses via an inverter, and that the logic outputs of said first and second D-type flip-flops are connected, respectively, to respective first inputs of first and second exclusive OR-gates, the outputs of which are connected to means for producing said control signal in accordance with the logic values at these gate outputs.
Claim 3
Dependent Claim
48 words
A phase sensitive detector as claimed in Claim 1, characterised in that the logic output of said first D-type flip-flop is also connected to a second input of the second exclusive OR-gate and a second input of the first exclusive OR-gate is connected to receive said data pulses.
Claim 4
Dependent Claim
107 words
A phase sensitive detector as claimed in Claim 1, characterised in that third and fourth D-type flip-flops are provided of which, the third has its D input connected to receive said data pulses, its clock input connected to receive said clock pulses via said inverter, and its logic output connected to the D input of said fourth D-type flip-flop which has its clock input connected to receive said clock pulses, the logic output-of said third D-type flip-flop being connected to a second input of said second exclusive OR-gate and the logic output of said fourth D-type flip-flop being connected to a second input of said exclusive OR-gate.
Claim 5
Dependent Claim
62 words
A phase sensitive detector as claimed in any preceding Claim, characterised in that said means for producing-said control signal comprises a capacitor the charge across which determines the value of the control signal, together with two current sources which are controlled respectively by the two gate outputs for one logic value thereof to drive current into and extract current from the capacitor.
Claim 6
Dependent Claim
113 words
A phase sensitive detector as claimed in Claim 4, characterised in that said two current sources are comprised by two transistor pairs of opposite conductivity type both pairs being connected as current . mirrors, the input transistor of each pair being connected to receive at its collector the logic output from a respective one of said two gates, one output with polarity inversion, and the other two transistors one from each pair, being connected in push-pull with their collectors connected together and to said capacitor, a respective resistor for determining the current magnitude in each current mirror transistor pair being connected between the collector of its input transistor and the respective gate output.
Claim 7
Dependent Claim
42 words
A phase sensitive detector as claimed in any preceding Claim, embodied in a data clock pulse generator in which the locally generated clock pulses are generated by a voltage-controlled oscillator which is controlled by said control signal to produce phase-corrected clock pulses.
Claim 8
Dependent Claim
52 words
A phase sensitive detector as claimed in any one of Claims 1 to 6, embodied in a data clock pulse generator in which locally generated clock pulses are generated by a crystal-controlled oscillator and are applied to a phase shifter which is controlled by said control signal to produce phase-corrected clock pulses.
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JPS54124612A
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