EP0054243A2
Expired / Lapsed
EP
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Memory controlling apparatus
Assignee: Hitachi Ltd
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Filing: 1981-12-08
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Granted: —
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Expires: 2001-12-08
Abstract
Abstract A memory controlling apparatus retains time information prepared based on performance of a memory and a processor, and determines timing of signal exchange between the memory and the processor based on the time information. An access time to the memory is reduced while maintaining a flexibility to a change of the access time due to increase of memory capacity or reconfiguration of the memory.
Inventors
- 👤 Kazutoshi Gemma
- 👤 Michiyasu Ishibashi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 18:12
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
69 words
A memory controlling apparatus for controlling signal exchange between a memory for storing data and a processor for processing the data accessed to said memory, comprising: means (20, 21) for retaining time information prepared based on performance of at least said memory and said processor; and means (27) for determining timing of said signal exchange by said processor based on at least said time information of said retaining means.
Claim 2
Dependent Claim
69 words
A memory controlling apparatus for controlling signal exchange between a memory for storing data and a processor for processing the data accessed to said memory, comprising: means (20, 21) for retaining time information prepared based on performance of at least said memory and said processor; and means (27) for determining timing of said signal exchange by said processor based on at least said time information of said retaining means.
Claim 3
Dependent Claim
18 words
A memory controlling apparatus according to Claim 1, wherein said memory controlling apparatus is located in said processor.
Claim 4
Dependent Claim
25 words
A memory processing apparatus according to Claim 1 or 2, wherein said timing determining means also determines timing of said signal exchange by said memory.
Claim 5
Dependent Claim
35 words
A memory controlling apparatus according to Claim 1, 2 or 3, wherein said timing determining means determines said timing of said signal exchange based on said time information and type of access to said memory.
Claim 6
Dependent Claim
35 words
A memory controlling apparatus according to Claim 1, 2, 3 or 4, wherein said retaining means retains an access time of memory cells of said memory and information concerning a machine cycle of said processor.
Claim 7
Dependent Claim
57 words
A memory controlling apparatus according to Claim 1, 2, 3, 4 or 5, wherein said timing determining means includes counter means for counting signals generated in synchronism with a machine cycle of said processor and produces a signal for indicating the timing of said signal exchange when the count of said counter means reaches a predetermined count.
References Cited (Backward Citations)
No citation records indexed.
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