EP0053958A1
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EP
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Process for the parallel/series conversion of a digital parallel sequence
Assignee: Thales SA
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Filing: 1981-11-13
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Granted: —
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Expires: 2001-11-13
Abstract
Abstract The process for the code conversion of eight parallel bits into words with nine series bits uses among the nine-bit words on the one hand those having five "1" and four "0" and which do not have five consecutive bits and whereof none starts or finishes with four identical bits, as well as their complements to 1, and on the other words having six "1" and three "0" with a maximum of transitions, as well as their complements to 1. Two complementary digital frame synchronization words are chosen from among the nine-bit words not retained for coding and which are not found in a random series of coded words.
Inventors
- 👤 Jean-Luc Grimaldi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 08:11
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/24; H04N7/52; H04N7/54; H04N7/56; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4906; H04L25/4908
Claims Analysis
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References Cited (Backward Citations)
US3215779A
Cited
GB1089551A
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GB1540617A
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GB1569076A
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GB2041702A
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GB2056225A
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