EP0052982A2
Expired / Lapsed
EP
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Semiconductor memory device and method for manufacturing the same
Assignee: Toshiba Corp
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Filing: 1981-11-11
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Granted: —
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Expires: 2001-11-11
Abstract
Abstract A semiconductor memory device having a MOS transistor with a floating gate (108a, 108b) capable of storing data. The MOS transistor has an erase gate (106) which overlaps part of the floating gate (108a, 108b) with an insulating film (110) interposed therebetween. Upon application of a high voltage on the erase gate (106), the field emission is caused between the floating gate (108a, 108b) and the erase gate (106) and the charge stored on the floating gate (108a, 108b) is removed.
Inventors
- 👤 Fujio Masuoka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 12:04
CPC Classifications
H; H10; H10B; H10B41/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
117 words
A semiconductor memory device comprising a semiconductor region of first conductivity type having an impurity region of second conductivity type; characterized in that a first conductive layer (106) is formed on said semiconductor region with a first insulating film (104b) interposed therebetween; a second conductive layer (108a to 108d) which is capable of storing data is formed on said semiconductor region with a second insulating film (102a to 102d) interposed therebetween; and a third conductive layer (114a, 114b) which is insulated from said first and second conductive layers is formed on said second conductive layer with a third insulating film (112) interposed therebetween; whereby charge is emitted from said second conductive layer through said first conductive layer.
Claim 2
Dependent Claim
117 words
A semiconductor memory device comprising a semiconductor region of first conductivity type having an impurity region of second conductivity type; characterized in that a first conductive layer (106) is formed on said semiconductor region with a first insulating film (104b) interposed therebetween; a second conductive layer (108a to 108d) which is capable of storing data is formed on said semiconductor region with a second insulating film (102a to 102d) interposed therebetween; and a third conductive layer (114a, 114b) which is insulated from said first and second conductive layers is formed on said second conductive layer with a third insulating film (112) interposed therebetween; whereby charge is emitted from said second conductive layer through said first conductive layer.
Claim 3
Dependent Claim
34 words
A semiconductor memory device according to claim 1, characterized in that said first conductive layer is an island surrounded by an insulating film, and said first conductive layer is connected to a wiring layer.
Claim 4
Dependent Claim
56 words
A semiconductor memory device according to claim 1 or 2, characterized in that said second and third conductive layers are formed on a substrate region where a channel is formed, said second conductive layer has a width smaller than a channel length, and said third conductive layer has a width not smaller than the channel length.
Claim 5
Dependent Claim
31 words
A semiconductor memory device according to any one of claims 1 to 3, characterized in that said first conductive layer is commonly formed for a plurality of said second conductive layers.
Claim 6
Dependent Claim
23 words
A semiconductor memory device according to claim 4, characterized in that said second conductive layer is arranged symmetrical about said first conductive layer.
Claim 7
Dependent Claim
37 words
A semiconductor memory device according to any one of claims 1 to 5, characterized in that part of said first conductive layer overlaps part of said second conductive layer with a fourth insulating film (110) interposed therebetween.
Claim 8
Dependent Claim
27 words
A semiconductor memory device according to claim 6, characterized in that the overlapping parts of said first and second conductive layers are present within a field region.
Claim 9
Dependent Claim
40 words
A semiconductor memory device according to claim 7, characterized in that part of said first insulating film which is interposed between said first conductive layer and said impurity region in said semiconductor region is thicker than said second insulating film.
Claim 10
Dependent Claim
22 words
A semiconductor memory device accroding to claim 6, characterized in that said first insulating film is thicker than said second insulating film.
Claim 11
Dependent Claim
33 words
A semiconductor memory device according to claim 9, characterized in that part of said second conductive layer is formed on part of said first conductive layer with said fourth insulating film interposed therebetween.
Claim 12
Dependent Claim
22 words
A semiconductor memory device according to claim 10, characterized in that said first insulating film is thicker than said fourth insulating film.
Claim 13
Dependent Claim
35 words
- 12. A semiconductor memory device according to claim 9, characterized in that part of said first conductive layer is formed on part of said second conductive layer with said fourth insulating film interposed therebetween.
Claim 14
Dependent Claim
30 words
A semiconductor memory device according to any one of the preceding claims, characterized in that said first conductive layer and said second conductive layer are both made of polycrystalline silicon.
Claim 15
Dependent Claim
30 words
A semiconductor memory device according to any one of claims 1 to 12, characterized in that said first conductive layer and said second conductive layer are both made of molybdenum.
Claim 16
Dependent Claim
60 words
A semiconductor memory device according to any one of the preceding claims, characterized in that a relation C FC > C FE ≧ C FC /5 is satisfied where C FE is a capacitance between said first conductive layer and said second conductive layer and C FC is a capacitance between said second conductive layer and said third conductive layer.
Claim 17
Dependent Claim
74 words
A semiconductor memory device according to any one of claims 1 to 14, characterized in that electrons are emitted from said second conductive layer by the field emission only if a potential of said first conductive layer is at high level and a potential of said third conductive layer is at low level, and charge stored on said second conductive layer may be quantitatively detected by varying the potential of said first conductive layer.
Claim 18
Dependent Claim
53 words
A semiconductor memory device according to claim 16, characterized in that a relation C FE ≧ C FC /5 is satisfied where C FE is a capacitance between said first conductive layer and said second conductive layer and C FC is a capacitance between said second conductive layer and said third conductive layer.
Claim 19
Dependent Claim
68 words
A semiconductor memory device according to claim 16, characterized in that a relation 5C FE ≧ C FC ≧ 2CFB is satisfied where C FE is a capacitance between said first conductive layer and said second conductive layer, C FC is a capacitance between said second conductive layer and said third conductive layer, and C FB is a capacitance between said second conductive layer and said semiconductor region.
Claim 20
Dependent Claim
32 words
A semiconductor memory device according to claim 18, characterized in that the capacitance C FE and the capacitance C FC satisfy a relation C FC > C FE ≧ C FC /5.
Claim 21
Dependent Claim
102 words
A semiconductor memory device according to any one of the preceding claims, characterized in that said impurity region consists of a source region and a drain region, for writing data, a predetermined voltage is applied across said source region and said drain region and voltages of the same polarity are applied to said first conductive layer and said third conductive layer, respectively, and for erasing data, said source region, said drain region and said third conductive layer are set at substantially the same potential, and a voltage of the same polarity as for writing data is applied to said first conductive layer.
Claim 22
Dependent Claim
36 words
A semiconductor memory device according to claim 20, characterized in that the voltage applied to said first conductive layer for erasing data is greater than the voltage applied to said first conductive layer for writing data.
Claim 23
Independent Claim
196 words
A method for manufacturing a semiconductor memory device characterized by comprising the steps of: selectively forming a first insulating film (104b) which is thick on a predetermined region of a semiconductor region of first conductivity type; diffusing an impurity in a predetermined surface region of said semiconductor region excluding said predetermined region for forming said first insulating film to form an impurity region of second conductivity type; thermally oxidizing said semiconductor region excluding said predetermined region for forming said first insulating film to form a second insulating film (102a to 102d) which is thin; selectively forming a first conductive layer (106) on said first insulating film; forming a third insulating film (110) on said first conductive layer; selectively forming a second conductive layer (108a to 108d) which extends from above said second insulating film excluding said second insulating film formed on said impurity region to said third insulating film, an end of said second conductive layer overlapping at least part of said first conductive layer with said third insulating film interposed therebetween; forming a fourth insulating film (112) on said second conductive layer; and forming a third conductive layer (114a, 114b) on said fourth insulating film.
Claim 24
Independent Claim
196 words
A method for manufacturing a semiconductor memory device characterized by comprising the steps of: selectively forming a first insulating film (104b) which is thick on a predetermined region of a semiconductor region of first conductivity type; diffusing an impurity in a predetermined surface region of said semiconductor region excluding said predetermined region for forming said first insulating film to form an impurity region of second conductivity type; thermally oxidizing said semiconductor region excluding said predetermined region for forming said first insulating film to form a second insulating film (102a to 102d) which is thin; selectively forming a first conductive layer (106) on said first insulating film; forming a third insulating film (110) on said first conductive layer; selectively forming a second conductive layer (108a to 108d) which extends from above said second insulating film excluding said second insulating film formed on said impurity region to said third insulating film, an end of said second conductive layer overlapping at least part of said first conductive layer with said third insulating film interposed therebetween; forming a fourth insulating film (112) on said second conductive layer; and forming a third conductive layer (114a, 114b) on said fourth insulating film.
Claim 25
Independent Claim
176 words
A method for manufacturing a semiconductor memory device characterized by comprising the steps of: selectively forming a first insulating film (104b) which is thick on a predetermined region of a semiconductor region of first conductivity type; selectively forming a first conductive layer (106) only on said first insulating film; forming a second insulating film (102a to 102d, 110) which is thin on said semiconductor region and said first conductive layer; selectively forming a second conductive layer (108a to 108d) on a predetermined region of said second insulating film so that an end of said second conductive layer may overlap at least part of said first conductive layer with said second insulating film (110) interposed therebetween; forming a third insulating film (112) on said second conductive layer; forming a third conductive layer (114a, 114b) on said third insulating film; diffusing an impurity in said semiconductor region to form an impurity region of second conductivity type using said third conductive layer as a mask; and forming a wiring layer (120d) which is connected to said first conductive layer.
Claim 26
Independent Claim
176 words
A method for manufacturing a semiconductor memory device characterized by comprising the steps of: selectively forming a first insulating film (104b) which is thick on a predetermined region of a semiconductor region of first conductivity type; selectively forming a first conductive layer (106) only on said first insulating film; forming a second insulating film (102a to 102d, 110) which is thin on said semiconductor region and said first conductive layer; selectively forming a second conductive layer (108a to 108d) on a predetermined region of said second insulating film so that an end of said second conductive layer may overlap at least part of said first conductive layer with said second insulating film (110) interposed therebetween; forming a third insulating film (112) on said second conductive layer; forming a third conductive layer (114a, 114b) on said third insulating film; diffusing an impurity in said semiconductor region to form an impurity region of second conductivity type using said third conductive layer as a mask; and forming a wiring layer (120d) which is connected to said first conductive layer.
References Cited (Backward Citations)
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