Pulse code modulation signal processing circuits

Claim 2

A PCM signal processing circuit comprising PCM data signal reproducing apparatus (18P), a memory (14) for storing said PCM data signal, a standardized signal input terminal for providing a standardized signal as a synchronizing signal for synchronizing said PCM data signal reproducing apparatus (18P), an address counter (38) for designating an address of said memory (14) to be read, and means for providing said address counter (38) with preset data in response to said standardized signal.

Claim 3

A PCM signal processing circuit according to claim 1 further comprising phase comparing means (31) for comparing in phase a word clock signal which is being synchronized with said standardized signal with another word clock signal which controls said memory (14) and for generating a detecting signal when phase synchronization of said word clock signal is obtained, and control means (36) for loading said preset data into said address counter (38) in response to said detecting signal.

Claim 4

A PCM signal processing circuit comprising a reproducing video recorder (18P), a data extracting circuit (23A) and a synchronizing signal separator circuit (23B) for receiving outputs of said reproducing video recorder (18P), a recording clock signal generator (34) for supplying a sync signal to said reproducing video recorder (18P), a word selector (12) connected to the output of said data extracting circuit (23A), a memory (14) for receiving the output of said word selector (12), a first counter (28), a first comparator (31) for receiving inputs from said first counter (28), a first switch (33) which in a first position connects the output of said recording clock signal generator (34) to said first comparator (31), a crystal oscillator (35), a controllable counter (27) for receiving inputs from said first comparator (31), a second switch (32) which in a first position supplies the output of said crystal oscillator (35) to said controllable counter (27), said first counter (28) being connected to receive an output of said controllable counter (27), and a read/write controller (36) for receiving an output from said first counter (28) and supplying inputs to said memory (14).

Claim 5

A PCM signal processing circuit comprising a reproducing video recorder (18P), a data extracting circuit (23A) and a synchronizing signal separator circuit (23B) for receiving outputs of said reproducing video recorder (18P), a recording clock signal generator (34) for supplying a sync signal to said reproducing video recorder (18P), a word selector (12) connected to the output of said data extracting circuit (23A), a memory (14) for receiving the output of said word selector (12), a first counter (28), a first comparator (31) for receiving inputs from said first counter (28), a first switch (33) which in a first position connects the output of said recording clock signal generator (34) to said first comparator (31), a crystal oscillator (35), a controllable counter (27) for receiving inputs from said first comparator (31), a second switch (32) which in a first position supplies the output of said crystal oscillator (35) to said controllable counter (27), said first counter (28) being connected to receive an output of said controllable counter (27), and a read/write controller (36) for receiving an output from said first counter (28) and supplying inputs to said memory (14).

Claim 6

A PCM signal processing circuit according to claim 3 including a third counter (30) for receiving the output of said first counter (28), a second comparator (24) for receiving inputs from said third counter (30) and said synchronizing signal separator (23B), and a controllable oscillator (26) for receiving the output of said second comparator (24) and supplying an output to said controllable counter (27) when said second switch (32) is in a second position.

Claim 7

A PCM signal processing circuit according to claim 4 including a low-pass filter (25) connected between said controllable oscillator (26) and said second comparator (24).

Claim 8

A PCM signal processing circuit according to claim 4 including a fourth counter (29) connected between said first and third counters (28, 30).

Claim 9

A PCM signal processing circuit according to claim 4 including a buffer counter (39) for receiving inputs from said read/write controller (36), an address counter (38) for receiving an input from said read/write controller (36), an address selector (37a, 37b) for receiving an output from said buffer counter (39), and an adder (42) for receiving outputs from said address counter (38) and said address selector (37a, 37b) and supplying an input to said memory (14).

Claim 10

A PCM signal processing circuit according to claim 7 wherein said address selector (37a, 37b) receives inputs from said word selector (12), and said first and fourth counters (28, 29) and supplies an input to said memory (14).

Claim 11

A PCM signal processing circuit according to claim 8 including a decoder (43) connected between certain inputs of said address selector (37a, 37b) and said word selector (12).

Claim 12

A PCM signal processing circuit according to claim 7 including an AND gate (41) for receiving inputs from said recording clock signal generator (34) and said first comparator (31), and a set pulse generator (40) for receiving the output of said AND gate (41) and supplying an output to said buffer counter (39).

Claim 13

A PCM signal processing circuit according to claim 10 wherein said set pulse generator (40) supplies inputs to said fourth counter (29).

Claim 14

A PCM signal according to claim 7 including an error-correction circuit (15) which receives the output of said memory (14).