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EP0051495A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

Ring scheduling apparatus for a digital multiplexed telecommunication system

Assignee: Ericsson Inc
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Filing: 1981-11-04
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Granted: —
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Expires: 2001-11-04
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Abstract

Abstract A ring scheduling apparatus for use in a digital multiplexed telephone communication system. The apparatus utilizes a controller (36) which sorts messages indicating which telephone lines are being run and what frequency and DC signal level is required for this ringing signal. The messages are sorted into voltage and frequency compatible groups. Digital data is then sent to a ring signal generating circuit (54, 42, 36, 88, 24, 66, 56, 44, 38, 26) to control the frequency of ring signal generated and the polarity of the DC signal upon which the ring signal is superimposed. A multiplexer (42, 44) and line interface circuitry for use in this system is included as well as a self-test circuit for testing the audio circuitry of idle telephone lines.

Inventors

  • 👤 Jay D. Hall
  • 👤 Theodore Michael Stump
  • 👤 Charles Wellington Thode

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-05 06:13
CPC Classifications
H; H04; H04Q; H04Q5/00; H04Q5/02; H04M; H04M19/00; H04M19/02; H04M19/023; H04Q11/00; H04Q11/04

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 120 words
A ring signal scheduling apparatus in a digital multiplexed telephone system serving a party line coupled to a plurality of telephones characterized by: digital circuitry (54, 42, 36, 88, 24, 66, 56, 44, 38, 26) for generating a variable ring signal, said ring signal having a first electrical characteristic during a first time period and a second electrical characteristic during a second time period; a first telephone coupled to said party line having ringer circuitry responsive to ring signals having said first electrical characteristic; a second telephone coupled to said party line having ringer circuitry responsive to ring signals having a second electrical characteristic; and control circuitry (24, 26, 36, 38) for connecting said ring signal to said party line.
Claim 2
Dependent Claim 120 words
A ring signal scheduling apparatus in a digital multiplexed telephone system serving a party line coupled to a plurality of telephones characterized by: digital circuitry (54, 42, 36, 88, 24, 66, 56, 44, 38, 26) for generating a variable ring signal, said ring signal having a first electrical characteristic during a first time period and a second electrical characteristic during a second time period; a first telephone coupled to said party line having ringer circuitry responsive to ring signals having said first electrical characteristic; a second telephone coupled to said party line having ringer circuitry responsive to ring signals having a second electrical characteristic; and control circuitry (24, 26, 36, 38) for connecting said ring signal to said party line.
Claim 3
Dependent Claim 18 words
An apparatus, as claimed in claim 1, wherein said variable characteristic of said ring signal includes its frequency.
Claim 4
Dependent Claim 30 words
An apparatus, as claimed in claim 1, wherein said variable characteristic of said ring signal includes the polarity of a D.C. voltage level upon which said ring signal is superimposed.
Claim 5
Dependent Claim 92 words
An apparatus, as claimed in claim 2 or 3 wherein said control circuitry (24, 26, 36, 38) includes circuitry for limiting to a predetermined number the number of telephones in a group of telephones responsive to ring signals having said first electrical characteristic which are coupled to said ring signal during said first time period and for limiting to a predetermined number the number of telephones in a group of telephones responsive to ring signals having said second electrical characteristic which are coupled to said ring s.ignal during said second time period.
Claim 6
Dependent Claim 129 words
An apparatus as claimed in claim 1, 2, 3 or 4, in which the digital circuitry for generating a variable ring signal includes: a clock; a source (408) of direct current voltage; a divider circuit (406) for controlling the frequency of said ring signal by dividing said clock signal by factor N; a relay (372) for controlling the polarity of direct current voltage which said ring signal has; and a controller (36, 38) for determining which telephones are to be rung, establishing the electrical characteristics of the ring signal which these telephones are responsive to and for controlling the frequency of said ring signal by establishing N for the divider circuit (406) and for controlling the direct current voltage polarity of the ring signal by controlling the relay (372).
Claim 7
Dependent Claim 47 words
. An apparatus as claimed in claim 5 further characterized in that the party line consists of a tip line and a ring line and said control circuitry (24, 26, 36, 38) controls whether said ring signal is applied to said tip line or said ring line.
Claim 8
Dependent Claim 43 words
An apparatus, as claimed in claim 5, wherein N is represented by a digital control word and said controller (36, 38) schedules the telephones to be rung into frequency and direct current voltage polarity compatible groups of a predetermined maximum number of telephones.
Claim 9
Dependent Claim 216 words
An apparatus as claimed in claim 1 wherein said digital circuitry (88) includes: a transformer (388) having a ring signal output (90) and a DC input (382) coupled to its secondary winding (386); an amplifier (424, 426, 418) having its output (600, 624) coupled to and driving the primary winding (432, 434) of said transformer; a signal generator (406, 412) having a control word input (32) for receiving digital data indicating the frequency of periodic waveform to be generated and having an output (420) coupled to the input of said amplifier; a latch (400, 366, 370) for storing control word data having a data output (404) coupled to the control word input of the signal generator and having a polarity data output (376) and having a data input (32) for receiving digital data indicating the desired frequency and polarity characteristics of said variable ring signal and an address and control input (46) for receiving signals indicating when data is to be loaded from said data input (32) into the latch (400, 366, 370); and a circuit (378, 372, 382) coupled to the polarity data output (376) of the latch and to the DC input (382) of the secondary winding (386) for controlling whether a positive or negative DC voltage is applied to the DC input (382).
Claim 10
Dependent Claim 732 words
An apparatus as claimed in claim 1 wherein said circuitry (88) includes: a transformer (388) having two primary windings (432, - 434) and a secondary winding (386) having an output (90) for a ring signal and having a DC input (382) for receiving a predetermined positive DC voltage or a predetermined negative DC voltage; an amplifier (424, 426) comprised of two Darlington pairs in push-pull operation, each pair driving one of the primary windings (432, 434) of the transformer (388) and each having a signal input (430, 428); two optical couplers (418) each coupled to the signal input (430, 428) of one of the Darlington pairs (424, 426) and each having a signal input (420); a power down circuit (416) having a signal.output (420) coupled to the signal input of the optical coupler (418) for lowering power dissipation in the optical coupler (418) and the Darlington pairs (424, 426) upon the appearance of a power down signal at a power down input (540) and having a signal input (414) for receiving a square wave ring signal and passing it through to said signal output in the absence of said power down signal; a square wave generator (412, 406) having a signal output (414) coupled to the signal input of the power down circuit and having an input.(408) for receiving a clock signal of a fixed frequency and a control word input (404) for receiving a digital control word which determines the frequency of the square wave generated by said square wave generator; a latch (400) having a data output (404) coupled to the control word input of the square wave generator and having a data input (32) for receiving digital data from said digital circuitry (36, 38) specifying the control word and having a clock input (402) for receiving a signal specifying when said input data is to be loaded, said latch (400) being arranged to store said input data and apply it as said control word to the control word input as said control word input (404) of the signal generator (406, 412); a decoder (374) having an address input (46) for receiving a plurality of binary address bits and having a plurality of enable outputs (402, 420, 376) one of which is coupled to the clock input of the latch (400), said decoder (374) being arranged to decode said address bits and to apply an enable signal to one of said enable outputs, said decoder (374) also having an enable input; a first circuit (392, 396) having a control signal input (364, 390) for receiving a control signal indicating when said decoder (374) is to be enabled and having an enable output (3.98) coupled to the enable input of said decoder, said first circuit (392, 396) being arranged to enable the decoder (374) upon receipt of a control signal from said digital circuitry (36, 38); a first flip-flop (422) having.a data input coupled to an on/off bit (482) at the data input of said latch (400) and having a clock input (420) coupled to an enable output of said decoder (374), and having an output (540) coupled to said power down input (540), said first flip-flop (422) being arranged to load the data of said on/off bit (482) upon receipt of an enable signal from said decoder (374) and store the data and apply it to said power down circuit (416) for causing said power down circuit (416) to lower power dissipation for one binary state of said on/off bit but not for the other; a second flip-flop (370) having a data input (368) coupled to a polarity indicating bit at the input of said latch (400) and having a clock input (376) coupled to an enable output of said decoder (374) for storing the binary state of said polarity bit upon receipt of an enable signal from said decoder (374) and for presenting it at a data output (376); a relay driver (378) having an input (376) coupled to said data output of said second flip-flop (370) and and having an output (380); and a relay (372) having its coil coupled to the output of said relay driver (380) and having a contact (382) alternately coupling said DC input (384) of the secondary winding (386) of the transformer (388) to either a positive DC voltage or a negative DC voltage depending upon the energization state of the relay coil.

References Cited (Backward Citations)

FR2129281A5 Cited
US3767857A Cited
US4192007A Cited

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