§
Luxuse
Patent Intelligence
Sign In
← Back to Patent Explorer
EP0051425A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

Bus access and priority resolving circuit

Assignee: Honeywell Inc
•
Filing: 1981-10-27
•
Granted: —
•
Expires: 2001-10-27
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A cumputer system has a bus, controlled by a CPU, which other units may want to access. Each such unit includes a bus access and priority resolving circuit. Gating circuit 14 is responsive to an IWANT signal indicating that the unit wants to access the bus, a no bus grant signal (BSGNT = 0), and a no bus request signal (BSREQ = 1), and the set state of a bus request flip-flop 24 to reset that flip-flop and thereby generate a bus request signal. The resetting of flip-flop 24 sets (via further gating means 112) an assert priority flip-flop 26, which enables priority logic 31' which resolves priority contentions with other units via a priority resolution bus 12. A bus grant signal (BSGNT = 1) from the CPU is combined with the priority logic output and the state of flip-flop 26, by logic circuitry 134, 176, 178, to generate an ISMNE signal (if the unit wins the priority contest) to grant the unit access to the bus.

Inventors

  • 👤 Steven A. Rose
  • 👤 Robert G. Cherry
  • 👤 Edward H. Forrester

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-02 20:19
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/368; G06F13/374

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 170 words
A bus access and priority resolving circuit (10) for a computer system unit (6) which may contend with other such units for access to a bus (8) controlled by a CPU (2), comprising: a bus request flip-flop (24) which generates a bus request signal (BSREQ) on the bus when reset; gating circuitry (14) responsive to a combination of conditions, including a signal (IWANT) indicating that the unit wants to access the bus and the absence of a bus request, to reset the bus request flip-flop; priority logic (31') which resolves priority contentions with other units; an assert priority flip-flop (26) which is set with the resetting of the bus request flip-flop to enable the priority logic; and logic circuitry (134,176,178) responsive to the priority logic and a bus grant signal (BSGNT) from the CPU to generate a signal (ISMNE) indicating that the unit is granted access to the bus, characterized by further gating means (112) responsive to the resetting of the bus request flip-flop to set the assert priority flip-flop.
Claim 2
Dependent Claim 170 words
A bus access and priority resolving circuit (10) for a computer system unit (6) which may contend with other such units for access to a bus (8) controlled by a CPU (2), comprising: a bus request flip-flop (24) which generates a bus request signal (BSREQ) on the bus when reset; gating circuitry (14) responsive to a combination of conditions, including a signal (IWANT) indicating that the unit wants to access the bus and the absence of a bus request, to reset the bus request flip-flop; priority logic (31') which resolves priority contentions with other units; an assert priority flip-flop (26) which is set with the resetting of the bus request flip-flop to enable the priority logic; and logic circuitry (134,176,178) responsive to the priority logic and a bus grant signal (BSGNT) from the CPU to generate a signal (ISMNE) indicating that the unit is granted access to the bus, characterized by further gating means (112) responsive to the resetting of the bus request flip-flop to set the assert priority flip-flop.
Claim 3
Dependent Claim 40 words
A circuit according to Claim 1, characterized in that the further gating circuitry (112) is fed by the complemented output (Q) of the bus request flip-flop (24) and via an inverter (108) with the direct output (Q) of that flip-flop.
Claim 4
Dependent Claim 23 words
A circuit according to either previous claim characterized in that the further gating circuitry (112) is fed by the assert priority flip-flop (26).
Claim 5
Dependent Claim 35 words
A circuit according to any previous claim characterized in that the assert priority flip-flop (26) has its reset input (R) fed from the computer system unit to ensure its resetting when the bus access ends.

References Cited (Backward Citations)

US4096569A Cited

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag