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EP0050434A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Communication device with under-run signalling

Assignee: Bull HN Information Systems Italia SpA
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Filing: 1981-10-05
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Granted: —
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Expires: 2001-10-05
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Abstract

Abstract A communication device comprises a microprocessor which feeds bytes to a universal synchronous receiver transmitter (USRT) 88. The USRT transmits the data serially, signal C2TXSO+. On an underrun (USRT empty before next byte in), the USRT transmits a sequence of flag bytes (01111110) and generates an underrun signal C2TXTXU+. This signal is fed to transmit underrun logic 92, where a shift register 350 generates a 1 signal which lasts long enough to convert the first two 0's in the flag byte sequence to 1's by OR gate 354. A sequence of 8 to 13 1's is therefore generated prior to the flag bytes, this 1 sequence indicating an underrun condition.

Inventors

  • 👤 Thomas O. Holtey
  • 👤 Steven S. Noyes
  • 👤 Richard P. Kelly
  • 👤 James C. Raymond

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-31 05:26
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/22; H04L1/0078; H04L1/0083; G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4221; G06F13/4226

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 105 words
A communication device comprising a microprocessor (76) and a universal synchronous receiver transmitter (USRT 88) which receives bytes in parallel from the microprocessor and transmits them serially, the USRT generating a sequence of flag bytes (01111110) and an underrun signal (C2TXTU+) if a fresh byte is not received from the microprocessor in time to maintain continuous transmission of data bits, characterized by transmit underrun logic (92) through which the transmitted bits from the USRT are passed, and which is responsive to the underrun signal to modify the start of the sequence of flag bytes to an underrun bit sequence (8 to 13 consecutive 1 bits).
Claim 2
Dependent Claim 105 words
A communication device comprising a microprocessor (76) and a universal synchronous receiver transmitter (USRT 88) which receives bytes in parallel from the microprocessor and transmits them serially, the USRT generating a sequence of flag bytes (01111110) and an underrun signal (C2TXTU+) if a fresh byte is not received from the microprocessor in time to maintain continuous transmission of data bits, characterized by transmit underrun logic (92) through which the transmitted bits from the USRT are passed, and which is responsive to the underrun signal to modify the start of the sequence of flag bytes to an underrun bit sequence (8 to 13 consecutive 1 bits).
Claim 3
Dependent Claim 57 words
A communication device according to Claim 1, characterized in that the transmit underrun logic includes a shift register (350) to which the underrun signal is fed and having a shifted output coupled to its shift control input (S1) which generates a 1 signal which adds two 1's to the first two 0's in the flag byte sequence.

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