EP0050037A2
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1981-10-13
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Granted: —
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Expires: 2001-10-13
Abstract
Abstract A static type semiconductor RAM device comprises a plurality of memory cells (MC) arranged at the crossing points of word lines (WD) and bit lines (B) with load circuits (Q 10 , Q 20 , ...) connected between the bit lines (B) and a voltage source (V DD ). The RAM device also includes a charging circuit (Q 110 , Q 120 , ...) which electrically charges all the bit lines (B) during the switching period of the word lines when all of the word lines (WD) are in a non-selected condition.
Inventors
- 👤 Atsushi Oritani
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 14:22
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/12; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
229 words
A semiconductor memory device comprising a plurality of word lines (WD 0 , WD 1 , ...) a plurality of bit lines (B 0 , B 0 , ... B M-1 , B M-1' ), a plurality of memory cells MC 0,0 , MC 0,1 , ...), arranged at the crossing points between the word lines (WD O , WD 1 , ...) and the bit lines (B 0 , B 0 , ... B M-1 , B M-1 ) and load circuits (Q 10 , Q 20 , Q 1(M-1) , Q 2(M-1) each connected between one of the bit lines B 0 , B 0 , ... B M-1 , B M-1 ) and a voltage source ( V DD ) the memory cell (MC 0,0 , MC 0,1 ) arranged at the crossing point of a particular word line and a particular bit line being selected by selecting that particular word line and that particular bit line, characterised in that a further charging circuit (Q 110 , Q 120 , ... Q 11(M-1) , Q 12(M-1) ) is provided which electrically charges all of the bit lines (B 0 , B 0 , ... B M-1 , B M-1 ) during the switching period of word line potentials when all of the word lines (WD O , WD 1 , ...) are in a non-selected state.
Claim 2
Dependent Claim
229 words
A semiconductor memory device comprising a plurality of word lines (WD 0 , WD 1 , ...) a plurality of bit lines (B 0 , B 0 , ... B M-1 , B M-1' ), a plurality of memory cells MC 0,0 , MC 0,1 , ...), arranged at the crossing points between the word lines (WD O , WD 1 , ...) and the bit lines (B 0 , B 0 , ... B M-1 , B M-1 ) and load circuits (Q 10 , Q 20 , Q 1(M-1) , Q 2(M-1) each connected between one of the bit lines B 0 , B 0 , ... B M-1 , B M-1 ) and a voltage source ( V DD ) the memory cell (MC 0,0 , MC 0,1 ) arranged at the crossing point of a particular word line and a particular bit line being selected by selecting that particular word line and that particular bit line, characterised in that a further charging circuit (Q 110 , Q 120 , ... Q 11(M-1) , Q 12(M-1) ) is provided which electrically charges all of the bit lines (B 0 , B 0 , ... B M-1 , B M-1 ) during the switching period of word line potentials when all of the word lines (WD O , WD 1 , ...) are in a non-selected state.
Claim 3
Dependent Claim
77 words
A memory device according to claim 1, wherein the further charging circuit includes means (Q 13 , Q 17 ) to detect the time period when the potentials of all the word lines (WD 0 , WD 1 , ...) are at the potential level of a non-selected state and to initiate the charging of all of the bit lines (B 0 , B 0 , . .. B M-1 , B M-1 ) at this time.
Claim 4
Dependent Claim
72 words
A memory device according to claim 1 or 2, --wherein the further charging circuit comprises a gate circuit (Q 13 - Q 17 ) which detects the potential levels of all of the word lines (WD 0 , WD 1 , ...) and a plurality of charging transistors (Q 110 , Q 120 , ... Q 11(M-1) , Q 12(M-1) which are controlled by the gate circuit (Q 13 -Q 17 ).
Claim 5
Dependent Claim
34 words
A memory device according to claim 3, wherein the gate circuit is a NOR gate having a plurality of input transistors (Q 14 - Q 17 ) and a load transistor (Q 13 ).
Claim 6
Dependent Claim
51 words
A memory device according to claim 3 or 4, wherein each of the charging transistors (Q 110 , Q 120 , ··· Q 11(M-1) , Q 12(M-1) ) is connected in parallel with one of the load circuits (Q 10 , Q 20 , ... Q 1(M-1) , Q 2(M-1). ).
Claim 7
Dependent Claim
46 words
- A memory device according to claim 3, 4 or 5, wherein the gate circuit (Q 13 - Q 17 ) detects the potential levels at the beginning portion and the end portion of each of the word lines (WD 0 , WD 1 , ...).
Claim 8
Dependent Claim
112 words
A memory device according to any one of claims 3 to 6, wherein the gate circuit is a NOR gate comprising a plurality of input transistors (Q 14 - Q 17 ) which is double the number of the word lines (WD O , WD l ) and a load transistor (Q 13 ) each of the input transistors (Q 14 - Q 17 ) being connected between the beginning portions of the word lines (WD 0 , WD 1 , ...) and the load transistor (Q 13 ) and between the end portion of the word lines (WD 0 , WD 1 , ...) and the load transistor (Q 13 ).
Claim 9
Dependent Claim
61 words
A memory device according to any one of the preceding claims, wherein each of the memory cells (MC) is a flip-flop type memory cell comprising a pair of cross coupled MIS transistors (Q 5 , Q6), a pair of transfer gate MIS transistors (Q 3 , Q 4 ) and a pair of load resistors (R 1 , R 2 ).
References Cited (Backward Citations)
No citation records indexed.
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