Static type semiconductor memory device

Claim 2

A static-type semiconductor memory device comprising a memory cell array having memory cells arranged at the crossing points of a plurality of word lines (X 0 , X 1 , ... X N-1 ) and a plurality of bit lines (Y 0' Y 1 , ... Y M-1 ), the memory cell array being divided into at least four memory cell blocks (BK 0 , BK 1 , BK 2 , BK 3 ) which are formed by divisions extending in a direction parallel to the word lines (X 0 ,X 1 , ... X N-1 ) and to the bit lines (Y 0 , Y 1 , ... Y M-l ) with each memory cell block (BK 0 , BK 1 , BK 2 , BK 3 ) including divided word lines (X 0 , X 0 ', ... X N-1 , X N-1) and divided bit lines (Y 0 , Y 0 ', ... Y M-1 , Y M'-1 ), the memory device also comprising a word decoder means (WD,WD') and a column decoder means (CD, CD') which are arranged to select only the divided word line (X 0 , X 0 ', ... X N-1 , X N'-1 ) and divided bit line (Y 0 , Y 0 ', ... Y M-1 , Y M'-1 ), respectively of the memory cell block containing the memory cell (MC) selected by a particular input address signal.

Claim 3

A static-type semiconductor memory device which comprises a memory cell array having memory cells arranged at crossing points of a plurality of word lines (X 0 , X 1 , ... X N-1 ), and a plurality of bit lines, (Y 0 , Y 1 , ... Y M -1) and a word (WD) and column decoder (CD), access to a selected memory cell being gained by selecting the word line and the bit line connected to the selected memory cell with input address signals, characterised in that the memory cell array is divided into a plurality of memory cell blocks (BK 0 , BK 1 , BK 2 , BK 3 ) which are formed by dividing the memory cell array in a direction parallel to the word lines (X 0 , X 1 , ... X N-1 ) and in a direction parallel to the bit lines (Y 0 , Y 1 ,...Y M-1 ) and in that each of the memory cell blocks (BK 0 , BK 1 , BK 2 , BK 3 ) comprises divided word lines (X 0 , X 0 ', . . . X N-1 , X N'-1 ) and divided bit lines (Y 0 , Y 0 ', ... Y M-1 , Y M'-1 ), the word decoder means (WD,WD') and the column decoder means (CD, CD') respectively, selecting only a divided word line and a divided bit line of the memory cell block containing the selected memory cell (MC).

Claim 4

A static-type semiconductor memory device which comprises a memory cell array having memory cells arranged at crossing points of a plurality of word lines (X 0 , X 1 , ... X N-1 ), and a plurality of bit lines, (Y 0 , Y 1 , ... Y M -1) and a word (WD) and column decoder (CD), access to a selected memory cell being gained by selecting the word line and the bit line connected to the selected memory cell with input address signals, characterised in that the memory cell array is divided into a plurality of memory cell blocks (BK 0 , BK 1 , BK 2 , BK 3 ) which are formed by dividing the memory cell array in a direction parallel to the word lines (X 0 , X 1 , ... X N-1 ) and in a direction parallel to the bit lines (Y 0 , Y 1 ,...Y M-1 ) and in that each of the memory cell blocks (BK 0 , BK 1 , BK 2 , BK 3 ) comprises divided word lines (X 0 , X 0 ', . . . X N-1 , X N'-1 ) and divided bit lines (Y 0 , Y 0 ', ... Y M-1 , Y M'-1 ), the word decoder means (WD,WD') and the column decoder means (CD, CD') respectively, selecting only a divided word line and a divided bit line of the memory cell block containing the selected memory cell (MC).

Claim 5

A memory device according to claim 1 or 2, wherein the word decoder means (WD, WD') comprises a plurality of word decoders (WD 0 , WD 1 , ...) each of which selects one of the divided word lines (X 0 , X 0 ', ... X N-1 , X N'-1 ) of one of the memory cell blocks (BK 0 , BK 1 , BK 2 , BK 3 ).

Claim 6

A memory device according to claim 3, wherein the word decoder means (WD, WD') further comprises a word block selector (WBS) which selects the one of the memory cell blocks using selection signals made from part of the input address signals.

Claim 7

A memory device according to any one of the preceding claims, wherein the column decoder means (CD, CD') comprises a plurality of column decoders (CD 0 , CD 1 , ... ), each of which selects one of the divided bit lines (Y 0 , Y 0 ', ... Y M-1 , Y M'-1 ) of the memory cell blocks (BK 0 , BK 1 , BK 2 , BK 3 ).

Claim 8

A memory device according to claim 5, wherein the column decoder means (CD, CD') further comprises a column block selector (CBS) which selects a group of the memory cell blocks disposed in the same column using part of the input address signals.

Claim 9

A memory device according to any one of the preceding claims, wherein the word decoder means (WD, WD')are arranged between the memory cell blocks (BK 0 , BK 1 , BK 2 , BK3).

Claim 10

A memory device according to any one of the preceding claims wherein the column decoder means (CD, CD') are arranged between the memory cell blocks (BK 0 , BK1, BK 2 , BK 3 ,).

Claim 11

A memory device according to any one of the preceding claims, wherein each of the memory cells comprises a pair of cross coupled MIS transistors, a pair of load elements connected between a voltage source and the pair of cross coupled MIS transistors, and a pair of transfer MIS transistors which are connected between the pair of cross coupled MIS transistors and a pair of divided bit lines, the gate electrodes of the pair of transfer MIS transistors being connected to the divided word line.

Claim 12

A memory device according to claim 9, wherein the divided bit lines are connected to a voltage source through bit line loads.

Claim 13

. A memory device according to any one of the preceding claims, wherein the memory device includes a sense amplifier (SA) which senses information from the selected memory cell (MC) and wherein only the divided bit line which is selected is connected to the sense amplifier (SA).