Semiconductor memory with improved data programming time

Claim 2

A semiconductor memory comprising: a memory array (1) with a plurality of memory cells (3 11 , 3 12 , ..., 3 21 , 3 22 , ...) arranged in a matrix form having column lines (2 0 , 2 1 , ...) and row lines, (1 0 , 1 1 , ...) and 1 bit output or bit outputs, a plurality of column lines being associated with each bit output; column and row decoders (4, 8) responsive to address signals to select a memory cell associated with each of bit outputs; data input circuit means (10) for writing data into a memory cell which is associated with each of bit outputs and selected by said column and row decoders; and means (5 0 , 5 1 , 5 2 , ...) responsive to a control signal (Yl, Y2) for simultaneously applying a program voltage to a plurality of said column lines; whereby a plurality of memory cells are simultaneously programmed, which are connected to said plurality of column lines to which the program voltage is applied and to one row line selected by said row decoder.

Claim 3

A semiconductor memory comprising: a memory array with a plurality of memory cells (311a, 31ma, 311b, ...) arranged in a matrix form having column lines (20a, 2ma, 20b, 2mb) and row lines (10a) and 1 bit output or bit outputs, a plurality of column lines being associated with each of bit outputs and said plurality of column lines being divided into a plurality of groups; column and row decoders (4a, 8a) responsive to address signals to select a memory cell which is associated with each of bit outputs; data input circuit means (l0a) for writing data into a memory cell which is associated with each of bit outputs and selected by said row and column decoders; and means (22a, 22b, 9a, 9b) responsive to a control signal (A0, AO) to cause said data input circuit means to apply a program voltage to corresponding column lines in different column line groups which are selected by said row decoder; whereby memory cells are simultaneously programmed, which are connected to corresponding column lines in different column line groups selected by said column decoder and to a row line selected by said row decoder.

Claim 4

A semiconductor memory comprising: a memory array with a plurality of memory cells (311a, 31ma, 311b, ...) arranged in a matrix form having column lines (20a, 2ma, 20b, 2mb) and row lines (10a) and 1 bit output or bit outputs, a plurality of column lines being associated with each of bit outputs and said plurality of column lines being divided into a plurality of groups; column and row decoders (4a, 8a) responsive to address signals to select a memory cell which is associated with each of bit outputs; data input circuit means (l0a) for writing data into a memory cell which is associated with each of bit outputs and selected by said row and column decoders; and means (22a, 22b, 9a, 9b) responsive to a control signal (A0, AO) to cause said data input circuit means to apply a program voltage to corresponding column lines in different column line groups which are selected by said row decoder; whereby memory cells are simultaneously programmed, which are connected to corresponding column lines in different column line groups selected by said column decoder and to a row line selected by said row decoder.

Claim 5

A semiconductor memory according to claim 1 or 2, in which said control signal is address signals of the same phase.

Claim 6

A semiconductor memory comprising: a plurality of memory arrays (32 1 , 32 2 , 32 3 , 32 4 ), each having a plurality of memory cells arranged in a matrix form with column lines and row lines and a plurality of bit outputs; decode means (33 1 , to 33 4 , 34 1 to 34 4 ) responsive to first address signals (A2 to A4) to select corresponding memory cells in a plurality of said memory arrays; a plurality of data write circuits (48 1 to 48 4 ) coupled to said memory arrays for writing data into corresponding memory arrays; a write-circuit selecting circuit (49) responsive to second address signals (A0, Al) to select one of said write circuits to write data into a corresponding memory array; and means (52, 53) responsive to a control signal (MW1, MWl, MW2, MW2) to modify said second address signals so as to cause said write-circuit selecting circuit to simultaneously select a plurality of said memory arrays.

Claim 7

A semiconductor memory comprising: a plurality of memory arrays (32 1 , 32 2 , 32 3 , 32 4 ), each having a plurality of memory cells arranged in a matrix form with column lines and row lines and a plurality of bit outputs; decode means (33 1 , to 33 4 , 34 1 to 34 4 ) responsive to first address signals (A2 to A4) to select corresponding memory cells in a plurality of said memory arrays; a plurality of data write circuits (48 1 to 48 4 ) coupled to said memory arrays for writing data into corresponding memory arrays; a write-circuit selecting circuit (49) responsive to second address signals (A0, Al) to select one of said write circuits to write data into a corresponding memory array; and means (52, 53) responsive to a control signal (MW1, MWl, MW2, MW2) to modify said second address signals so as to cause said write-circuit selecting circuit to simultaneously select a plurality of said memory arrays.

Claim 8

A semiconductor memory according to claim 4, in which said decode means comprises column and row decoders provided for each of said memory arrays.

Claim 9

A semiconductor memory comprising: a memory array (1) having a plurality of memory cells (311a, 3lma, 311b, ...) arranged in a matrix form with column lines (20a, 2ma, 20b, 2mb) and row lines (10a) and a plurality of bit outputs, a plurality of said column lines being associated with each of bit outputs and divided into a plurality of groups; column and row decoders (4a, 8a) responsive to address signals to select corresponding column lines in different column line groups associated with each bit output and a row line; a plurality of switching means (9a, 9b) for, when enabled, connecting each of said column line groups to a program power source; data input circuit means (10b) responsive to input data having more than two voltage levels to selectively control said plurality of switching means, whereby data are simultaneously written into memory cells connected to column lines selected by said column decoder and a row line selected by said row decoder.

Claim 10

A semiconductor memory comprising: a memory array (1) having a plurality of memory cells (311a, 3lma, 311b, ...) arranged in a matrix form with column lines (20a, 2ma, 20b, 2mb) and row lines (10a) and a plurality of bit outputs, a plurality of said column lines being associated with each of bit outputs and divided into a plurality of groups; column and row decoders (4a, 8a) responsive to address signals to select corresponding column lines in different column line groups associated with each bit output and a row line; a plurality of switching means (9a, 9b) for, when enabled, connecting each of said column line groups to a program power source; data input circuit means (10b) responsive to input data having more than two voltage levels to selectively control said plurality of switching means, whereby data are simultaneously written into memory cells connected to column lines selected by said column decoder and a row line selected by said row decoder.

Claim 11

A semiconductor memory according to claim 6, in which the number of the voltage levels of said input data is 2 n when the number of the column line groups for one bit output is n.

Claim 12

A semiconductor memory according to claim 6, wherein said input data is data for writing a plurality of memory cells having a plurality of addresses according to different voltage levels.

Claim 13

A semiconductor memory according to claim 1, 2, 4 or 6, in which each of said memory cells is a floating-gate type MOS transistor having its gate connected to a row line and its drain connected to a column line.

Claim 14

A semiconductor memory comprising: a memory array having a plurality of memory cells arranged in a matrix form having column lines and row lines and one bit output or bit outputs, a plurality of column lines being associated with each bit output; column and row decoders responsive to address signals to select a memory cell associated with each of bit outputs; data input circuit means for writing data into a memory cell which is associated with each of bit outputs and selected by said column and row decoders; and means responsive to a control signal for simultaneously applying a program voltage to a plurality of said row lines; whereby a plurality of memory cells are simultaneously programmed, which are connected to said plurality of row lines to which the program voltage is applied and a column line selected by said column decoder.

Claim 15

A semiconductor memory comprising: a memory array having a plurality of memory cells arranged in a matrix form having column lines and row lines and one bit output or bit outputs, a plurality of column lines being associated with each bit output; column and row decoders responsive to address signals to select a memory cell associated with each of bit outputs; data input circuit means for writing data into a memory cell which is associated with each of bit outputs and selected by said column and row decoders; and means responsive to a control signal for simultaneously applying a program voltage to a plurality of said row lines; whereby a plurality of memory cells are simultaneously programmed, which are connected to said plurality of row lines to which the program voltage is applied and a column line selected by said column decoder.

Claim 16

A semiconductor memory comprising: a memory array having a plurality of memory cells arranged in a matrix form having column lines and row lines and one bit output or bit outputs, a plurality of column lines being associated with each bit output; column and row decoders responsive to address signals to select a memory cell associated with each of bit outputs; data input circuit means for writing data into a memory cell which is associated with each of bit outputs and selected by said column and row decoders; and means responsive to a control signal for simultaneously applying a program voltage to a plurality of column lines and a plurality of row lines; whereby a plurality of memory cells are simultaneously programmed, which are connected to said plurality of column lines and said plurality of row lines which are supplied with the program voltage.

Claim 17

A semiconductor memory comprising: a memory array having a plurality of memory cells arranged in a matrix form having column lines and row lines and one bit output or bit outputs, a plurality of column lines being associated with each bit output; column and row decoders responsive to address signals to select a memory cell associated with each of bit outputs; data input circuit means for writing data into a memory cell which is associated with each of bit outputs and selected by said column and row decoders; and means responsive to a control signal for simultaneously applying a program voltage to a plurality of column lines and a plurality of row lines; whereby a plurality of memory cells are simultaneously programmed, which are connected to said plurality of column lines and said plurality of row lines which are supplied with the program voltage.

Claim 18

A semiconductor memory according to claim 4, 10 or 11, wherein said control signal is address signals of the same phase.

Claim 19

A semiconductor memory according to claim 10 or 11, wherein said control signal is address signals of the same phase, and said address signals of the same phase are produced by address buffers supplied with address signals and controlled by a signal applied through an input pad.

Claim 20

A semiconductor memory according to claim 10 or 11, wherein said control signal is address signals of the same phase, which are produced by address buffers supplied with address signals and controlled by a circuit having an input logic 1 level different from a logic 1 level of a signal input.

Claim 21

A semiconductor memory according to claim 1, 2, 4, 6, 10 or 11, further comprising means for simultaneously applying program data to a plurality of memory cells.

Claim 22

A semiconductor memory comprising: a memory array having a plurality of memory cells arranged in a matrix form having column lines and row lines and one bit output or bit outputs, a plurality of column lines being associated with each bit output; column and row decoders responsive to address signals to select a memory cell which is associated with each of bit outputs; data input circuit means for writing data into a memory cell selected by said column and row decoders; means for programming a plurality of memory cells for each of bit outputs; and means for simultaneously applyig program data for programming said plurality of memory cells.

Claim 23

A semiconductor memory comprising: a memory array having a plurality of memory cells arranged in a matrix form having column lines and row lines and one bit output or bit outputs, a plurality of column lines being associated with each bit output; column and row decoders responsive to address signals to select a memory cell which is associated with each of bit outputs; data input circuit means for writing data into a memory cell selected by said column and row decoders; means for programming a plurality of memory cells for each of bit outputs; and means for simultaneously applyig program data for programming said plurality of memory cells.

Claim 24

A semiconductor memory according to claim 16, wherein said means for applying program data includes means for determining program data of said plurality of memory cells in response to an input voltage of said data input circuit means.

Claim 25

A semiconductor memory according to claim 16, wherein said means for applying program data is controlled by a control signal.

Claim 26

A semiconductor memory according to claim 18, wherein said control signal is address signals of the same phase.

Claim 27

A semiconductor memory according to claim 19, wherein said address signals are produced by address buffers supplied with address signals and controlled by a signal supplied through an input pad.

Claim 28

A semiconductor memory according to claim 19, wherein said address signals of the same phase are produced by address buffers supplied with address signals and controlled by a circuit having an input logic 1 level different from a logic 1 level of a signal input.