EP0049988A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
High speed data transfer for a semiconductor memory
Assignee: Inmos Corp
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Filing: 1981-10-05
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Granted: —
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Expires: 2001-10-05
Abstract
Abstract A system for rapidly transferring data between a plurality of successive memory locations and a data output buss (10) includes a plurality of data latches (A 0 , A 1 , A 2 , A 3 ) for storing data derived from successive memory locations. A corresponding plurality of serially coupled decoders (D 0 , D 1 , D 2 , D 3 ) are each associated with one of the data latches (A 0 - A 3 ). In response to an address input, one decoder (Do) is enabled for causing its associated data latch (A 0 ) to output its stored data to the data buss (10). The one decoder (D 0 ) then disables itself and enables the next decoder (D 1 ) so that a second data latch (A 1 ) outputs its stored data. The procedure is continued such that the data latches (A 0 - A3) are caused to sequentially output their stored data. In addition, each of the decoders (D 0 - D 3 ) is associated with one of a plurality of input buffers (B 0 , B 1 , B 2 , B 3 ) and the decoders (D 0 - D 3 ) are arranged to cause the input buffers (B 0 - B 3 ) to sequentially write input data into successive memory locations.
Inventors
- 👤 Sargent Sheffield Eaton, Jr.
- 👤 David Rudolph Wooten
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 23:54
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/10; G11C7/00; G11C7/10; G11C7/1015; G11C7/103; G11C7/1033; G11C7/1045; G11C7/1051; G11C7/106; G11C7/1066; G11C8/04; G11C8/18
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
246 words
A system for rapidly transferring data between a plurality of successive memory locations of a semi-conductor memory and a data output buss characterised in that said system comprises a plurality of N data latches (A 0 ,A 1 ,A 2 ,A 3 ) for storing data associated with N successive memory locations which are defined by a plurality of bits of the address input, a corresponding plurality of N serially connected decoders (D 0 ,D 1 ,D 2 ,D 3 ) each associated with one of said data latches, each decoder (D 0 ,D 1 ,D 2 ,D 3 ) being arranged to be enabled for causing its associated data latch to output its stored data to the data output buss (10), and each decoder receiving selected bits of the address input such that one of the decoders (DO) is initially enabled, in response to said selected bits having a given logic state, for causing its associated data latch (A 0 ) to output its stored data to the data output buss, the enabled decoder (DO) being arranged to then disable itself and to enable a successive decoder (D 1 ), the latter decoder (D l ) and each remaining decoder (D 2 ,D 3 ) being arranged to disable itself after having been enabled and to enable a successive decoder so as to cause the data latches to output, to the data buss, N successive bits of data in response to a single address input.
Claim 2
Independent Claim
246 words
A system for rapidly transferring data between a plurality of successive memory locations of a semi-conductor memory and a data output buss characterised in that said system comprises a plurality of N data latches (A 0 ,A 1 ,A 2 ,A 3 ) for storing data associated with N successive memory locations which are defined by a plurality of bits of the address input, a corresponding plurality of N serially connected decoders (D 0 ,D 1 ,D 2 ,D 3 ) each associated with one of said data latches, each decoder (D 0 ,D 1 ,D 2 ,D 3 ) being arranged to be enabled for causing its associated data latch to output its stored data to the data output buss (10), and each decoder receiving selected bits of the address input such that one of the decoders (DO) is initially enabled, in response to said selected bits having a given logic state, for causing its associated data latch (A 0 ) to output its stored data to the data output buss, the enabled decoder (DO) being arranged to then disable itself and to enable a successive decoder (D 1 ), the latter decoder (D l ) and each remaining decoder (D 2 ,D 3 ) being arranged to disable itself after having been enabled and to enable a successive decoder so as to cause the data latches to output, to the data buss, N successive bits of data in response to a single address input.
Claim 3
Dependent Claim
79 words
A system according to Claim 1, characterised in that a plurality of input buffers (B 0 ,B 1 ,B 2 ,B 3 ) are provided for writing input data into memory locations, each of said decoders (D 0 ,D 1 ,D 2 ,D 3 ) being associated with an input buffer, and in that said decoders are responsive to a single address input for selecting said buffers sequentially so as to write the input data into successive memory locations.
Claim 4
Dependent Claim
64 words
A system according to claim 2 characterised in that each buffer (B O -B 3 ) includes an input (126,128) for receiving data, an output (130,132) for coupling data to memory, and means (166,168) for holding the data at its output (130,132) while successive buffers are selected such that writing of the data at a buffer output may continue while successive buffers are selected.
Claim 5
Dependent Claim
41 words
A system according to Claim 2 or 3, characterised in that each buffer (B O -B 3 ) includes a hold-off circuit (172-183; 184-196) for rendering the buffer insensitive to data received at its input while its associated decoder is disabled.
Claim 6
Independent Claim
123 words
A system according to any preceding claim characterised in that each decoder (Do-D 3 ) includes an address-input circuit (50,52,108,109) receiving the selected address bits for developing an output signal (Y i ) in response to the selected address bits being in a given logic state, -means (40) for coupling said output signal (Y i ) to an associated data latch for causing said data latch to output its stored data, and a disabling circuit (58,86,88,94,96,110) coupled to receive the output signal developed by the address-input circuit and a clock signal, and being responsive to said control signal and to the clock signal for inhibiting the address-input circuit from developing a further output signal, whereby each decoder disables itself after having been enabled.
Claim 7
Dependent Claim
69 words
A system according to claim 5 characterised in that each decoder further includes an enabling circuit (60,104,106) coupled to said address-input circuit, receiving the output signal of a previous decoder and said clock signal, and responsive to the previous decoders output signal and the occurrence of said clock signal for enabling its address-input circuit to develop an output signal, whereby each decoder is enabled by a previously enabled decoder.
Claim 8
Dependent Claim
235 words
A system according to claim 5 or claim 6, characterised in that said address-input circuit (50,52,108,109) includes a first node (64) adapted to be precharged to a positive voltage level, transistor means (50,52) receiving the address input bits for inhibiting the discharge of said first node in response to said address bits being in said given logic state; a first transistor (66) having a source coupled to said first node (64) having a gate receiving a second clock signal (φ 0D2 ), and having a drain coupled to a second node (68), a second transistor (108) having a gate coupled to the second node (68), having a drain receiving a third clock signal (φ Y0 ), and a source output terminal (54) for developing the control signal thereat, said second clock signal (φ 0D2 ) being selected to go high to turn on the first transistor (66) and precharge said second node (68), and then to go low so as to substantially cut off said first transistor (66) and thereby isolate said first node (64) from said second node (68), said second clock signal (φ 0D2 ) being selected to go high while said first transistor (66) is substantially cut off, to bootstrap said second node (68) to a higher voltage via gate to drain capacitance associated with said second transistor (108) and to drive the output terminal (54) to a relatively high positive voltage.
Claim 9
Independent Claim
184 words
A system according to any preceding claim for a semi- conductor memory having a read mode and a write mode, characterised in that the data latches comprise four data latches (A O ,A l ,A 2 ,A 3 ) arranged to ouput their stored data when selected by an enabled decoder (D 0 ,D 1 ,D 2 ,D 3 ) in that the system includes four data input buffers (B 0 ,B 1 ,B 2 ,B 3 ) each having an input (126, 128) for receiving incoming data, an output (130,132) for coupling the data to memory, and each being arranged to output the data to memory when selected by an enabled decoder, and in that the decoders include four serially connected decoders (D 0 ,D 1 ,D 2 ,D 3 ) each associated with one of the data latches and with one of the input buffers, and each being responsive to its address input for selecting its associated data latch when the memory is in a read mode and for selecting its associated input buffer when the memory is in a write mode.
References Cited (Backward Citations)
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