EP0049158A2
Expired / Lapsed
EP
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I/O data processing system
Assignee: Bull HN Information Systems Inc
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Filing: 1981-09-29
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Granted: —
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Expires: 2001-09-29
Abstract
Abstract A data processing system includes a communication subsystem having an I/O microprocessor for communicating with a central processing unit and a main memory; and a line microprocessor for communicating with a number of devices. The 1/0 microprocessor and the line microprocessor communicate with each other through mailboxes stored in a shared memory 44. The line microprocessor is controlled by a PROM 58 and channel control programms (CCP's) in a RAM 60, and uses a work RAM 52 for data storage; the 1/0 microprocessor is controlled by a PROM 38 and uses a work RAM 40 for data storage. The line microprocessor interrupts the I/O microprocessor to process data bytes being transferred between main memory and a device requesting service when the line microprocessor has responded to the requesting device and loaded the mailbox.
Inventors
- 👤 Kin C. Yu
- 👤 Gary J. Goss
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 05:12
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/38; G06F13/382; G06F13/385; G06F15/00; G06F15/16; G06F15/163; G06F15/167
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
131 words
A data processing system for transferring data bytes comprising a main memory (4) coupled via a system bus (16) to a communication multiplexer (10) coupled to a plurality of input/ output devices (18-24) for transferring data bytes between the main memory and the input/output devices, characterized in that the communication multiplexer comprises: shared memory means (44) for storing address and control information and the data bytes; line microprocessor means (56) responsive to one of the input/ output devices requesting service during a polling operation to transfer data bytes between the shared memory means and the input/ output device, and having first means for generating a first interrupt signal; and I/O microprocessor.means (36) responsive to the first interrupt signal for transferring data bytes between the shared memory means and the main memory.
Claim 2
Dependent Claim
131 words
A data processing system for transferring data bytes comprising a main memory (4) coupled via a system bus (16) to a communication multiplexer (10) coupled to a plurality of input/ output devices (18-24) for transferring data bytes between the main memory and the input/output devices, characterized in that the communication multiplexer comprises: shared memory means (44) for storing address and control information and the data bytes; line microprocessor means (56) responsive to one of the input/ output devices requesting service during a polling operation to transfer data bytes between the shared memory means and the input/ output device, and having first means for generating a first interrupt signal; and I/O microprocessor.means (36) responsive to the first interrupt signal for transferring data bytes between the shared memory means and the main memory.
Claim 3
Dependent Claim
56 words
The system of claim 1 characterized in that the shared memory means comprises: mailbox means for storing the data bytes and control information; and channel control block means for storing a plurality of addresses identifying locations in the main memory for storing data bytes received from or being transferred to each of the input/ output devices.
Claim 4
Dependent Claim
106 words
The system of claim 2 characterized in that the control information comprises: a receive channel number or transmit channel number indicative of the communication multiplexer receiving data bytes from or transmitting data bytes to the input/output device; a load command indicative of the input/ output device requesting a data byte from the main memory; a store command indicative of the input/output device transferring data byte to the main memory; and a flag bit in a first state- indicative of the mailbox means being available to the line microprocessor means, and in a second state indicative of the mailbox means being available to the I/O microprocessor means.
Claim 5
Dependent Claim
88 words
The system of claim 3 characterized in that the channel control block means is responsive to the receive channel number to identify the input/output device for selecting a first of the addresses for writing a first data byte received from the input/output device into a first location in the main memory, and responsive to the transmit channel number to identify the input/output device for selecting a second of the addresses for reading a byte from a second location of the main memory for transfer to the input/output device.
Claim 6
Independent Claim
111 words
The system of either of claims 3 and 4 characterized in that the line microprocessor means comprises: a line microprocessor; second means responsive to a ready signal indicating an input/output device requesting service during the polling operation for generating a second interrupt signal for interrupting the line microprocessor, the line microprocessor being responsive to the receive channel number for storing the store command,the data byte, and the receive channel number in the mailbox means when the flag bit is in the first state, and generating the flag bit in the second state; the first means being responsive to selected address signals from the line microprocessor for generating the first interrupt signal.
Claim 7
Independent Claim
240 words
The system of anyoneof claims 3 to 5 characterized in that the I/O microprocessor means comprises an I/O microprocessor; third means coupled to the first means and responsive to the first interrupt signal for generating a third interrupt signal for interrupting the I/O microprocessor, the I/O microprocessor being coupled to the mailbox means when the flag bit is in the second state for reading the receive channel number, the store command and the data byte or the transmit channel number and the load command, the channel control block means being coupled to the I/0 microprocessor and responsive to the receive channel number for transferring the first of the addresses to the main memory via the system bus, the I/O microprocessor being responsive to the store command for transferring the first of the data bytes to the main memory via the system bus for storage in the first location indicated by the first of the addresses, the channel control block means being responsive to the transmit channel number for transferring the second of the addresses to the second location in the main memory via the system bus, the I/O microprocessor being responsive to the load command for transferring a preassigned channel number to the main memory via the system bus, the main memory transferring the second of the data bytes to the I/O microprocessor for storage in the mailbox means, that I/O microprocessor setting the flag bit to the first state.
Claim 8
Dependent Claim
34 words
The system of claim 6 characterized in that the line microprocessor is responsive to the flag bit in the first state for transferring a data byte from the mailbox means to the input/output device.
Claim 9
Independent Claim
15 words
The system of any previous claim characterized in that the first means is a decoder.
Claim 10
Independent Claim
17 words
The system of any previous claim characterized in that the second means comprises a bistable logic element.
Claim 11
Independent Claim
17 words
The system of any previous claim characterized in that the third means comprises a bistable logic element.
References Cited (Backward Citations)
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