Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
135 words
A memory array comprising a plurality of recirculating loop memory elements (1, 2 ... N), said elements being clocked in synchronism so that the corresponding bits recirculate in their respective loops with the same time phase, characterized by a shift register (7) having a number of cells (1', 2' ... N') equal in number to the number of said elements, first means (17, 27, 29) for selectively connecting each said cell to a respective one of said elements for writing data into said elements, second means (16, 30, 32) for selectively connecting each said cell to a respective one of said elements for reading data from said elements, and means (13, 15) for shifting data stored in said shift register throughout said number of cells in the time interval between successive clockings of said elements.
Claim 2
Dependent Claim
135 words
A memory array comprising a plurality of recirculating loop memory elements (1, 2 ... N), said elements being clocked in synchronism so that the corresponding bits recirculate in their respective loops with the same time phase, characterized by a shift register (7) having a number of cells (1', 2' ... N') equal in number to the number of said elements, first means (17, 27, 29) for selectively connecting each said cell to a respective one of said elements for writing data into said elements, second means (16, 30, 32) for selectively connecting each said cell to a respective one of said elements for reading data from said elements, and means (13, 15) for shifting data stored in said shift register throughout said number of cells in the time interval between successive clockings of said elements.
Claim 3
Dependent Claim
17 words
The memory array of claim 1, wherein the elements (1, 2 ... N) are charge coupled devices.
Claim 4
Dependent Claim
28 words
The memory array of claim 1, further including third means (31, 47) independent of the shift register (7) for writing data into the elements (1, 2 ... N).
Claim 5
Dependent Claim
31 words
The memory array of claim 1, further including fourth means (50, 49, 36-38) independent of the shift register (7) for reading data from the elements (1 , 2 ... N) .
Claim 6
Dependent Claim
24 words
The memory array of claim 3, further including means (13) for operating the first and third means (17, 27, 29 and 31, 47) alternatively.
Claim 7
Dependent Claim
25 words
The memory array of claim 4, further including means (13) for operating the second and fourth means (16, 30, 32 and 50, 49, 36-38) alternatively.