EP0048229A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Arrangement in a radar system for correction of phase and amplitude errors in a video signal
Assignee: Telefonaktiebolaget LM Ericsson AB
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Filing: 1981-09-04
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Granted: —
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Expires: 2001-09-04
Abstract
Abstract An arrangement is provided for correcting the phase and amplitude errors occurring in the quadrature detector of a Doppler radar system. A correction unit (KE) is connected to both analogue-digital converters (AD1, AD2) in the I and Q channels to receive a radar signal which has been received by the system antenna and phase-detected in the quadrature detector (FD1, FD2, FS). The output of the correction unit (KR) is connected to a regulating network (RN) for sensing the output signals from the correction unit (KE) and controlling the latter so that the amplitude and phase errors (a' and θ') will be zero.
Inventors
- 👤 Erik Ragnar Arvidsson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 21:13
CPC Classifications
H; H03; H03D; H03D1/00; H03D1/22; H03D1/2245; G; G01; G01S; G01S13/00; G01S13/02; G01S13/50; G01S7/00; G01S7/02; G01S7/28; G01S7/285
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
295 words
1 Arrangement in the receiver of a coherent radar system for correcting phase and amplitude errors occurring when the incoming signal is divided into two quadrature channels in the system signal receiver, there being arranged a quadrature detector for said division of the incoming signal, an analogue-digital converter for converting the signals divided in the quadrature detector to corresponding digital values, and a correction unit for multiplying and adding the divided signals by, and to a first and second correction signal derived from said phase and amplitude errors, characterized by a regulating network (RN) for forming the first and the second correction signal, said network containing two regulating loops, of which one Loop contains a multiplier unit (M5, M7) for forming the product signal from the signals (S and S Q ) from the correction unit (KE) in the respective channels (I and Q), a summator unit (S1, R4) and a first comparator unit (JF1, JF3) for at Least establishing the polarity of the product signal after the signal has been formed, a first register unit (R1, T1; R4) for forming a value of the correction signal answering to the phase error in response to the polarity established by the first comparator circuit, the second- loop contains two quantity value-forming units (B1, B2 or B3, B4) and,an adding circuit (A3, A4) for forming a difference signal between the quantities of said signals (S I and S Q ) from the correction unit (KE), a second comparator circuit (JF2, JF4) for establishing the polarity of said difference signal, a second register unit (R2, D1, D2, M6 and R3) for forming a value of the correction signal answering to the amplitude error in response to what polarity has been estabLished by the second comparator circuit (JF2, JF4).
Claim 2
Dependent Claim
295 words
1 Arrangement in the receiver of a coherent radar system for correcting phase and amplitude errors occurring when the incoming signal is divided into two quadrature channels in the system signal receiver, there being arranged a quadrature detector for said division of the incoming signal, an analogue-digital converter for converting the signals divided in the quadrature detector to corresponding digital values, and a correction unit for multiplying and adding the divided signals by, and to a first and second correction signal derived from said phase and amplitude errors, characterized by a regulating network (RN) for forming the first and the second correction signal, said network containing two regulating loops, of which one Loop contains a multiplier unit (M5, M7) for forming the product signal from the signals (S and S Q ) from the correction unit (KE) in the respective channels (I and Q), a summator unit (S1, R4) and a first comparator unit (JF1, JF3) for at Least establishing the polarity of the product signal after the signal has been formed, a first register unit (R1, T1; R4) for forming a value of the correction signal answering to the phase error in response to the polarity established by the first comparator circuit, the second- loop contains two quantity value-forming units (B1, B2 or B3, B4) and,an adding circuit (A3, A4) for forming a difference signal between the quantities of said signals (S I and S Q ) from the correction unit (KE), a second comparator circuit (JF2, JF4) for establishing the polarity of said difference signal, a second register unit (R2, D1, D2, M6 and R3) for forming a value of the correction signal answering to the amplitude error in response to what polarity has been estabLished by the second comparator circuit (JF2, JF4).
Claim 3
Dependent Claim
115 words
2 Arrangement as claimed in claim 1, characterized in that the correction unit (KE) comprises a first multiplier (M1, M4) for multiplying the signal across one channel (the I' channel) by the first correction signal (a'θsinθ' for Figure 3, tan ' for Figure 4) corresponding to the phase error, an adding circuit (A1, A2) for forming the difference between the signal in the second channel (the Q' channel) and the output signal from the first multiplier, a second multiplier (M2, M3) before (Figure 4) or after (Figure 3) said adder circuit, for multiplying the signal at the second channel (the Q channel) by the second correction signal (1/a l cosθ') corresponding to the amplitude error.
Claim 4
Dependent Claim
67 words
3 Arrangement as claimed in claims 1-2, characterized in that the multiplier (M5) incorporated in one Loop of the regulating network is connected to a summator (S1), and in that the signal thus formed is compared in said comparator unit (JF1) with a constant value, the contents of said first register unit (R1) being varied in response to the result of the comparison in said comparator unit.
Claim 5
Dependent Claim
77 words
4 Arrangement as claimed in claims 1-2, characterized in that the multiplier (M7) incorporated in one loop of the regulating network is directly connected to said comparator unit (JF3) so that the signal formed in the multiplier (M7) is compared with a constant value in the comparator unit (JF3), the contents in said first register unit (R4) being varied in time with the input signal rate to the multiplier, whereby the register unit constitutes said summator unit.
References Cited (Backward Citations)
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