Laminated ceramic sheet printed circuit components including capacitance means

Abstract

Abstract A laminated ceramic sheet printed circuit carrier (1) for supporting semiconductor integrated circuit chips (11) has a coefficient of thermal expansion matched to that of the chips (11) as well as a high value of capacitance. The carrier (1) provides both mechanical and electrical connections to the chip (11). The carrier (1) contains a matrix of dot capacitors (9) formed between laminated layers (2) of ceramic material. In some cases, conductive layers are provided on the upper and lower surfaces of a thin film of ceramic material in which dielectric bodies are interspersed in an array of openings therein. The resultant ceramic dielectric combination has a coefficient of thermal expansion which matches the coefficient of thermal expansion of the silicon chip and the substrate thereby relieving stress upon the solder ball joints between the interposer and both the chip and the substrate. This minimizes the mechanical stress upon the solder ball joints during thermal cycling of the structure. Alternatively, an array of multilayer ceramic capacitors has an array of dielectric bodies located within holes in ceramic layers between capacitor plates, or entire arrays of capacitors are formed in the space between ceramic sheets. <??>In addition to its principal application in a chip carrier, other applications are in chip interposers and discrete capacitors for mounting on chip carriers.

Inventors

• 👤 Christopher Henry Bajorek
• 👤 Dudley Augustus Chance
• 👤 Chung Wen Ho

Bibliographic Details