Data processing apparatus including a BSM validation facility

Claim 2

Data processing apparatus having at least one central processor (CPU), main storage formed of a plurality of sets of at least one basic storage module (BSM) per set, a service processor, a service interface between each BSM set and the service processor, a processing interface between each BSM set and the CPU(S) and BSM validation facility characterised in that the BSM validation facility comprising a self-sequencing BSM tester (SV) in and for each BSM set interfacing with the service processor via the service interface and fencing gates in each processing interface to disable that interface, control of the fencing gates being exercised by the service processor via the service interface.

Claim 3

Apparatus as claimed in claim 1 wherein each BSM set is served by its own BSM controller (BSC) having data and command bus systems (see Fig: 2 between system controller and BSM array board including CMD REG: DATA REG: ODD REG: EVEN REG):, the fencing gates spanning the bus systems at the processing interface, the BSM tester of the set having corresponding bus systems connecting with the BSC bus systems between the fencing gates and the BSM(S) of the set, a fencing trigger (Fig. 2, FNCT) being provided in the service interface and coupled to the fencing gates in such a way that the set/reset state of the fencing trigger is determined by the service processor and determines the enabled/disabled states of the fencing gates controlling which interface is currently operative with respect to the BSM(S) of the set.

Claim 4

Apparatus as claimed in claim 2 in which the BSM tester includes a BSM selection mechanism 101 (if, or in case, there is more than one BSM in the set), an expected data register (103), an actual data register 102, an address generator (104, 107), a comparator (21) and control logic (Figs. 5D, H and J), the comparator being arranged to provide a miscompare output when the contents of the expected and actual data registers do not match, the actual data register receiving data from the controller bus system and the expected data register, feeding data to the controller bus system, the address generator feeding addresses to the controller bus system, and the control logic being operable to:- (a) when invoked by the service process, cause the writing of data from the expected data register into that location indicated by the address generator, the reading of that location into the actual data register, the comparing of the contents of the registers (102, 103) and the generation of a next address for an automatic next test cycle; (b) stop the test cycles and signal an interrupt to the service processor on detection of a miscompare output from the comparator; and (c) stop the test cycles and signal an interrupt to the service processor on detection, in terms of an overflow or an underflow from the address generator, of the attainment of a boundary address in the BSM being tested.

Claim 5

Apparatus as claimed in claim 3 in which the BSM tester includes a marker mask register (105) settable by the service processor, the control logic being arranged to resume testing cycles at that address indicated by the contents of the marker mask register after an interrupt has been signalled.

Claim 6

Apparatus as claimed in claim 3 wherein the address generator includes a line address register (104) for addressing a line of double words in the BSM identified in the BSM identifier register, the data registers (102, 103) receiving or outputting in parallel all bits in a line, a double word counter (106) for addressing any double word in the line contained in the line data register, and the control logic includes a sequence counter (109) for clocking operations of the BSM tester and a direction mode register (107) for indicating the direction of addressing by the address generating means, whereby the direction mode register may be set to control address incrementing, decrementing or holding of an address value by the address registering means to aid in the detection of addressing errors.

Claim 7

Apparatus as claimed in claim 5 in which the control logic includes a suboperation counter (108) to register each suboperation to be performed by the validation means, one state of the suboperation counter operationally disconnecting the validation means from all BSMs in the associated BSM set, and other states of the suboperation counter operationally connecting the validation means to the BSM identified in the BSM identifier register to control different types of tests defined by different contents of the suboperation register, and a suboperation decoder (FIG. 51) to decode the state in the suboperation counter to control the suboperation to be performed by the validation means, suboperation logic circuits (FIG. 5H) to increment the suboperation counter through a predetermined sequence of states determined by an initial setting of the suboperation counter, the suboperation decoder including suboperation decoding circuits sensing the states of the suboperation counter and the state of the direction mode register to control a predetermined group of suboperations of the validation means, including means to compare a first expected bit pattern with an actually read bit pattern of each unit read in the BSM, means to store the complement of the first expected bit pattern in each unit after the unit is read and compared by the comparing means, means to increment the address in the BSM after each complement of the first bit pattern is stored by the storing means, means for detecting when one addressing end of the BSM is reached and to change the state of the direction mode register to decrement the addressing of the BSM, means for providing a second expected bit pattern which is the complement of the first expected bit pattern, the comparing means comparing the second expected bit pattern with an actually read bit pattern of each unit read in the BSM, the storing means storing the complement of the second expected bit pattern in each unit after the unit is read and compared by the comparing means, means to decrement the address in the BSM after each complemented second bit pattern is stored by the storing means, the detecting means detecting when another addressing end of the BSM is reached, whereby forward and backward addressing errors are detected by the comparing means miscomparing the expected bit pattern with a read bit pattern which may be the complement of the expected bit pattern in either direction of addressing the BSM.

Claim 8

Apparatus as claimed in claim 5 in which level sensitive scan design (LSSD) technology ircuits are used to construct and serially connect to a command scan-in/scan-out line from the service processor the BSM identifier register, the address registering means, the marker mask register, the direction mode register, the suboperation counter, the expected data register and the actual data register, whereby the counter and registers can transmit signals and receive signals on the command scan-in/scan-out line under control of the service processor to test a BSM not constructed of LSSD technology, a scope loop trigger (111) being provided in LSSD technology and being connected serially with the counter and registers, the scope loop trigger for being set and reset by service processor command, means for disabling all signals for stopping the incrementing or decrementing of the address register means, the disabling means being connected to the output of the scope loop trigger, whereby the tester can be arranged to continuously cycle through the BSM addresses regardless of any miscompare output from the comparing means or any output from the underflow/overflow means.

Claim 9

Apparatus as claimed in any of claims 5 to 7 including error detecting logic, the system being arranged to respond to the detecting of an uncorrectable error (UE) in a BSM using error detection hardware in the BSM by interrupt signalling to the CPU and to the service processor the occurrence of a UE and the identity of the BSM having the UE and in the service maintaining in the service processor a count of the detected UEs in each BSM, and to respond to the detecting that the maintained count has reached a threshold, by moving errorless and error-corrected data out of the BSM to another BSM or to I/O, invoking the BSM tester with respect to that BSM to fence of that BSM set and to exercise every cell in the BSM a plurality of times to validate error free and correctable areas in the BSM and to outputting the identity of each field replacement part of the BSM having a UE and removing electrical power from that BSM.