EP0044924A2
Expired / Lapsed
EP
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Physical address developing unit and method
Assignee: NEC Corp
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Filing: 1981-06-05
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Granted: —
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Expires: 2001-06-05
Abstract
Abstract The problem underlying the invention is the construction of a physical address in a main memory unit whose field is divided into a plurality of segments, with a comparatively small number of address bits defined by an instruction and with a high addressing capability without imposing any restriction on the conventional programs. This problem is solved by a physical address developing unit with a plurality of base registers (50), a plurality of segment base address registers (40), a plurality of segment number registers (60), instruction storing means for storing a given instruction, and first and second address developing means for developing a tentative and a final physical address respectively. A method for developing a physical address with the above developing unit is also described (Fig. 3A).
Inventors
- 👤 Nariaki Hirano
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 13:14
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0615; G06F12/0223; G06F12/0292; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/342
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
301 words
A physical address developing unit, particularly at a central processing unit, for accessing a main memory unit (30) whose field is divided into at least one segment (SO...S2), said address developing unit comprising: a) a plurality of base registers (50;BRO...BR15) for storing a plurality of offset addresses allotted for said at least one segment (SO...S2); b) a plurality of segment base address registers (40; SBARO...SBAR15) for storing at least one segment base address allotted for said at least one segment (SO...S2); c) a plurality of segment number registers (60;SNRO... SNR15) provided in one-to-one correspondence to said segment base address registers (40;SBARO...SBAR15) for storing the numbers allotted for each of said segment base address registers (40;SBARO...SBAR15); d) instruction storing means (18,20,32,30,16) for storing a given instruction with a first field for indicating the number of one of said plurality of base registers (50;BRO...BR15) and the number of one of said plurality of segment number registers (60;SNRO...SNR15) and a second field for indicating the displacement from the base address stored in said one base register (50; BRO...BR15) designated by the first field; e) first address developing means (14,50,22,100,21,23) for developing a tentative physical address for accessing said main memory unit (30) by the sum of the base address of the base register (50;BRO...BR15) designated by said first field of the given instruction and the displacement of said second field of the instruction; and f) second address developing means (14,60,13,40,22,100, 23,19) for developing a final physical address for accessing said main memory unit (30) by the sum of the tentative physical address given from said first address developing means and the segment base address in said one segment base address register (40;SBARO...SBAR15) designated by the number of said one segment number register (60;SNRO...SNR15) which is designated by said first field of the given instruction.
Claim 2
Dependent Claim
301 words
A physical address developing unit, particularly at a central processing unit, for accessing a main memory unit (30) whose field is divided into at least one segment (SO...S2), said address developing unit comprising: a) a plurality of base registers (50;BRO...BR15) for storing a plurality of offset addresses allotted for said at least one segment (SO...S2); b) a plurality of segment base address registers (40; SBARO...SBAR15) for storing at least one segment base address allotted for said at least one segment (SO...S2); c) a plurality of segment number registers (60;SNRO... SNR15) provided in one-to-one correspondence to said segment base address registers (40;SBARO...SBAR15) for storing the numbers allotted for each of said segment base address registers (40;SBARO...SBAR15); d) instruction storing means (18,20,32,30,16) for storing a given instruction with a first field for indicating the number of one of said plurality of base registers (50;BRO...BR15) and the number of one of said plurality of segment number registers (60;SNRO...SNR15) and a second field for indicating the displacement from the base address stored in said one base register (50; BRO...BR15) designated by the first field; e) first address developing means (14,50,22,100,21,23) for developing a tentative physical address for accessing said main memory unit (30) by the sum of the base address of the base register (50;BRO...BR15) designated by said first field of the given instruction and the displacement of said second field of the instruction; and f) second address developing means (14,60,13,40,22,100, 23,19) for developing a final physical address for accessing said main memory unit (30) by the sum of the tentative physical address given from said first address developing means and the segment base address in said one segment base address register (40;SBARO...SBAR15) designated by the number of said one segment number register (60;SNRO...SNR15) which is designated by said first field of the given instruction.
Claim 3
Dependent Claim
30 words
Unit according to Claim 1, characterised in that the field of each of the segment base address registers (40; SBARO...SBAR15) is greater than the field of the tentative physical address.
Claim 4
Dependent Claim
57 words
Unit according to Claim 1 or 2, characterised in that the field of each of the segment base address registers (40;S B ARO...SBAR15) is a 24-bit field, the field of each of the base registers (50;BRO...BR15) and of the tentative physical address is a 16-bit field and the displacement field of the instruction is a 12-bit field.
Claim 5
Dependent Claim
103 words
A physical address developing method, particularly to be carried out by a unit according to any of Claims 1 to 3, the physical address being based on an instruction comprising an address with a designation field R and a displacement field, characterised in that a) an offset address as a tentative physical address is constructed by adding a base address selected by the content of the designation field R to the displacement contained in the displacement field, and b) the physical address is constructed by adding the offset address to a segment base address selected by the content of the designation field R.
Claim 6
Dependent Claim
31 words
Method according to Claim 4, characterised in that the base address is the content of one of a plurality of base registers (50;BRO...BR15) selected by the content of the field R.
Claim 7
Dependent Claim
74 words
Method according to Claim 4 or 5, characterised in that the segment base address is the content of one of a plurality of segment base address registers (40;SBARO... SBAR15), the respective segment base address register (SBARO ... SBAR15) being selected by the content of one of a plurality of segment number registers (60;SNRO...SNR15), the respective segment number register (SNRO...S NR 15) being selected by the content of the designation field R of the instruction.
References Cited (Backward Citations)
No citation records indexed.
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