EP0044713A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Circuit arrangements for processing digital data
Assignee: Toshiba Corp
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Filing: 1981-07-16
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Granted: —
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Expires: 2001-07-16
Abstract
Abstract A circuit arrangement for processing analog audio data into a format for transmitting, receiving and playing back in a video format, the arrangement comprising an analog-to-digital converter (12) for receiving the analog audio data, a large scale integration circuit (10) with clock, read-write, input, output, chip select, data and address terminals for receiving the output of the converter (12), a random access memory (25) connected to the read-write, data and address terminals of the large scale integration circuit (10), a tri-state buffer circuit (30) coupled to supply outputs to data terminals (Do to D 3 ) αf the large scale integration circuit (10) and to receive an input from one of the chip select terminals (CS 3 ), and switches (31 to 34) connected to the tri-state buffer circuit (30).
Inventors
- 👤 Susumu Hoshimi
- 👤 Tadashi Kojima
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 16:01
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/06; G11C5/066; G11B; G11B20/00; G11B20/10; G11B20/10527; G11B20/12; G11B20/1201; G11B20/1207; G11B20/1208; G11B2020/10537; G11B2020/10546; G11B2220/00; G11B2220/90
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
140 words
A circuit arrangement for processing analog audio data into a format for transmitting, receiving and playing back in a video format, the arrangement comprising: an analog-to-digital converter (12) for receiving said analog audio data; a large scale integration circuit (10) with clock, read-write, input, output, chip select, data and address terminals, for receiving the output of said analog-to-digital converter (12); a random access memory (25) connected to said read-write, data and address terminals of said large scale integration circuit (10); a first tri-state buffer circuit (30) coupled to supply outputs to certain (DO to D 3 ) of said data terminals of said large scale integration circuit (10) and to receive an input from one of said chip select terminals (CS 3 ); and a first plurality of switches (31 to 34) connected to said first tri-state buffer circuit (30).
Claim 2
Dependent Claim
140 words
A circuit arrangement for processing analog audio data into a format for transmitting, receiving and playing back in a video format, the arrangement comprising: an analog-to-digital converter (12) for receiving said analog audio data; a large scale integration circuit (10) with clock, read-write, input, output, chip select, data and address terminals, for receiving the output of said analog-to-digital converter (12); a random access memory (25) connected to said read-write, data and address terminals of said large scale integration circuit (10); a first tri-state buffer circuit (30) coupled to supply outputs to certain (DO to D 3 ) of said data terminals of said large scale integration circuit (10) and to receive an input from one of said chip select terminals (CS 3 ); and a first plurality of switches (31 to 34) connected to said first tri-state buffer circuit (30).
Claim 3
Dependent Claim
35 words
A circuit arrangement according to claim 1 wherein said first tri-state buffer (30) can take a high or low signal output state depending upon the conditions of said first plurality of switches (31 to 34).
Claim 4
Dependent Claim
32 words
A circuit arrangement according to claim 2 wherein said first tri-state bufer (30) can take a floating output signal state when it receives an input from said one chip select terminal (CS3).
Claim 5
Dependent Claim
28 words
A circuit arrangement according to claim 3 including an oscillator (16) which supplies clock inputs to said large scale integration circuit (10) and to said analog-to-digital converter (12).
Claim 6
Dependent Claim
54 words
A circuit according to any one of the preceding claims including a second tri-state buffer circuit (36) connected to certain (DO to 06) of said data terminals and a chip select terminal (CS l ) of said large scale integration circuit (10), and a microcomputer (37) connected to said second tri-state buffer circuit (36).
Claim 7
Dependent Claim
87 words
A circuit according to claim 5 including a playback input terminal (41) for receiving a playback signal, a sync separator (20) connected to said playback input terminal (20), a first dubbing input switch (18) connected to said sync separator (20), said oscillator (16) and to said clock terminal of said large scale integration circuit (10), a playback large scale integration circuit (40) for receiving an output of said sync separator (20) and a second randon access memory (45) connected to said playback large scale integration circuit (40).
Claim 8
Dependent Claim
39 words
A circuit according to claim 6 including a second dubbing/input switch (14) connected to said analog-to-digital converter (12), to said playback large scale integration circuit (40) and to the input terminal SD. of said large scale integration circuit (10).
Claim 9
Dependent Claim
39 words
A circuit according to claim 7 including a third dubbing/input switch (21) connected to said oscillator (16) to change the frequency of the clock signal to said large scale integration circuit (10) for NTSC and PAL television signal formats.
Claim 10
Dependent Claim
31 words
A circuit according to claim 7 including a latch circuit (46) connected to said playback large scale integration circuit (40), and a second microcomputer (47) connected to said latch circuit (46).
Claim 11
Dependent Claim
37 words
A circuit according to claim 9 including a third tri-state buffer circuit (50) with a plurality of switches (51 to 54) connected to said second random access memory (45) and said playback large scale integration circuit (40).
References Cited (Backward Citations)
US4211997A
Cited
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