Method for making a self-aligned field effect transistor integrated circuit structure

Claim 2

Self-aligned field effect transistor integrated circuit structure, characterized by a silicon body (2); a pattern of narrow dimensioned dielectric regions (26) on a major surface of said body; a gate dielectric layer (28) on said major surface of said body forming a portion of said field effect transistor integrated circuit between certain of said narrow dimensioned regions; PN junction source/drain regions (19) located directly under certain portions of said narrow dimensioned regions (26) and associated with a channel under said gate dielectric layer (28); doped polycrystalline silicon gate electrodes (30) on the surface of said gate dielectric layer (28) between said certain of said narrow dimensioned regions (26); and metal electrical contacts (34) made to the edges of said PN junction regions (19) while filling the spaces between the remaining said narrow dimensioned regions and which contacts are self-aligned to said narrow dimensioned regions (26) and substantially planar with the tops of said narrow dimensioned regions.

Claim 3

Circuit structure of claim 1, characterized in that silicon dioxide regions (10) within said body (2) isolate said transistors from one another.

Claim 4

Circuit structure of claim 2, characterized in that said source/drain regions (19) are in said silicon body (2) below the said certain of said narrow dimensioned regions (26) and said metal electrical contacts (34) are made to the edge of said source/drain regions.

Claim 5

Method for forming the structure as claimed in claims 1 to 3, characterized by providing a silicon body (2); forming a highly doped first polycrystalline silicon layer (18) contiguous to said body in designated active device areas and dielectrically isolated from said body in other areas; forming a silicon nitride insulating layer (20) above the said polycrystalline silicon layer (18); forming openings in said silicon nitride layer (20) and said polycrystalline silicon layer (18) by reactive ion etching in the areas designated to be the gate regions of said integrated circuits which results in the structure having substantially horizontal surfaces and substantially vertical surfaces with the surface of said silicon body exposed in the designated gate areas; outdiffusing using a heat cycle the said dopant from said polycrystalline silicon layer (18) into said body (2) to form the source/drain regions (19) for said field effect integrated circuit; forming a conformal insulating layer on both said substantially horizontal surfaces and said substantially vertical surfaces; reactive ion etching said conformal insulating layer to substantially remove said conformal layer from said horizontal surfaces, both from above the said polycrystalline silicon layer (18) and said surface of the silicon body (2) exposed in the designated gate areas, and to provide said narrow dimensioned dielectric regions (26) on said silicon body (2); thermally oxidizing said surface of the silicon body exposed between certain of said narrow dimensioned regions to form the gate dielectric regions (28) for the said integrated circuits; forming a highly doped second polycrystalline silicon layer (30) on the designated said gate dielectric regions (28) for said field effect transistor integrated circuits wherein said layer is the gate electrode for said circuits; removing the remaining said silicon nitride layer (20) and said first polycrystalline silicon layer (18) by etching to leave the said narrow dimensioned regions (26) and said second polycrystalline silicon layer (30) on said gate dielectric regions (28) on said silicon body (2); and forming a conductive layer (34) on said silicon body (2) which has portions thereof electrically separated by said narrow dimensioned regions (26) for contacting the said source/drain regions (19).

Claim 6

Method of forming the structure as claimed in claims 1 to 3 having a short-channel field effect transistor, characterized by providing a silicon body (2) having monocrystalline silicon regions dielectrically isolated from similar regions at a major surface of said body; providing a substantially vertically sided silicon dioxide mask (44) located over the said major surface of at least some of said monocrystalline silicon regions; reactively ion etching the exposed said monocrystalline silicon to a depth of between about 0.4 to 1.5 micrometers; ion implanting a dosage of oxygen into the exposed said monocrystalline silicon at low energy and annealing the structure to form a silicon dioxide layer (46) covering the horizontal said exposed monocrystalline silicon regions while allowing the vertically exposed said monocrystalline silicon to remain exposed; forming on said major surface of said silicon body a doped polycrystalline silicon layer (18) substantially the same thickness as said silicon dioxide mask (44) in all areas other than the locations of said silicon dioxide mask; ion implanting a dosage of nitrogen at low energy and annealing the structure to form a silicon nitride layer (20) covering said doped polycrystalline silicon layer (18); heating the structure to diffuse impurities through said vertically exposed monocrystalline silicon to form PN source/drain regions (19) therein; etching away said silicon dioxide mask (44) to provide substantially vertical and substantially horizontal surfaces on the structure and with openings to the surface of said monocrystalline silicon regions; depositing a first conformal insulating coating (22) on both said substantially vertical and substantially horizontal surfaces; reactive ion etching said first conformal insulating coating to substantially remove said first conformal coating from said horizontal surfaces and to provide narrowed said openings therebetween due to presence of said insulating coating on the vertical surfaces of said monocrystalline silicon regions; forming a short-channel region (24) through said narrowed openings; etching away said first conformal insulating coating (22) on the vertical surfaces; depositing a second conformal insulating coating (26) on both said substantially vertical and substantially horizontal surfaces; reactive ion etching said second conformal coating (26) to substantially remove said second conformal coating from said horizontal surfaces and to provide narrow dimensioned dielectric regions (26) on said silicon body; thermally oxidizing the surface of said monocrystalline silicon between certain of said narrow dimensioned regions (26) to form the gate dielectric regions (28) for said integrated circuit; forming a highly doped second polycrystalline silicon layer (30) on the designated said gate dielectric regions (28) for said field effect transistor integrated circuits wherein said layer is the gate electrode for said circuits; removing the remaining said first polycrystalline silicon layer (18) by reactive ion etching to leave the said narrow dimensioned regions (26) and said second polycrystalline silicon layer (30) on said gate dielectric (28) on said silicon body (2); and forming a conductive layer (34) on said silicon body (2) which has portions thereof electrically separated by said narrow dimensioned regions (26) for contacting the said source/drain regions (19).

Claim 7

Method of the claims 4 and 5, characterized in that a P channel (24) is ion implanted into said silicon body prior to said thermally oxidizing the said surface to form the gate dielectric regions (28).

Claim 8

Method of one or several of the claims 4 to 6, characterized in that said source/drain regions (19) are formed in said silicon body (2) below the said certain of said narrow dimensioned regions (26) and said conductive layer (34) contacts the edges of said source/drain regions (19).

Claim 9

Method of one or several of the claims 4 to 7, characterized in that the said forming a second polycrystalline layer (30) includes blanket depositing a plastic material (31) over the said second polycrystalline layer (30) to planarize the surface, reactive ion etching the plastic material (31) and said second polycrystalline silicon layer (30) until said silicon nitride layer (20) is reached, removing the remaining plastic (31) by oxygen ashing and oxidizing the surface of the remaining said second polycrystalline silicon gate electrode (30) to form a silicon dioxide layer (32) thereover.

Claim 10

Method of claim 9, characterized in that said narrow dimensioned regions (26) and portions of said silicon dioxide (32) on the surface of said second polycrystalline silicon layer (30) are removed so that portions of said conductive layer (34) can make electrical contact to said gate electrode.

Claim 11

lO. Method of one or several of the claims 4 to 9, characterized in that the said forming a conductive layer includes depositing a layer (34) of aluminum over said narrow dimensioned regions (26) and areas in between, blanket depositing a plastic material (35) over the said aluminum layer (34) to planarize the surface, reactive ion etching the said plastic material (35) and said aluminum layer (34) until the tops of said narrow dimensioned regions (26) are reached and removing the remaining said plastic material (35).

Claim 12

Method of one or several of the claims 4 to lO, characterized in that said polycrystalline gate electrode (30) is electrically contacted on its edge by a conductive layer of the same material and formed at the same time as said conductive layer (34) for contacting said source/drain regions (19).

Claim 13

Method of one or several of the claims 4 to 10, characterized in that said polycrystalline silicon gate elctrode (30) is electrically contacted by a higher level metal electrical contact from above.