EP0042967A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Mutiple data flow component system
Assignee: International Business Machines Corp
•
Filing: 1981-05-19
•
Granted: —
•
Expires: 2001-05-19
Abstract
Abstract A Large Scale Integration (LSI) data flow component is described for use as a building block, the component being capable of use singly or in combination to provide data flow paths and functions of different data widths for a processor or microprocessor. A component with an eight-bit data flow is described as a "byte slice", wherein individual byte control (5) is provided within a multiple-byte configuration so that single data flow components within the group can operate independently of other components under control of external logic. Components may operate on a stand-alone, a multiple-byte, or nonactive-byte basis. A control scheme permits functions of one component to be influenced by actions or logic of another component to permit efficient implementation of arithmetic algorithms.
Inventors
- 👤 Donald Egbert Doyle
- 👤 George Arlen Helwarth
- 👤 Jack Leo Quanstrom
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 22:31
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7896
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
281 words
A data flow component for use as an element in a processor or microprocessor system comprising a data bus structure (1, 2) for use in transfer of data as input or output to said data flow component, an instruction register (3), an instruction bus (4) for providing instruction to said instruction register, an Arithmetic-Logic Unit (12) for performing arithmetic operations, a pair of operand register A and B (8, 9), a special register Q (10) for use as an extension to a selected one of said operand registers for multiply, divide, and extended shift instructions, a status register (11), a high speed shifter (13), said shifter through selected gating providing a single or multiple shift capability in a single timing interval, a bidirectional carry bus structure (6, 7) for high end and low end carries resulting from arithmetic or shift operations. This data flow component is characterized in that it further comprises: slice function control lines (5) for determining the state of said component and in particular its stand-alone, active or nonactive state; a test and control logic unit (17) connected to the instruction register (3) and to the slice function control lines (5) for acting on instructions related to said data flow component operations and for providing control and test signals pertaining to said data flow component; a carry bypass bus (18) controlled by said test and control logic (17) for providing direct path for carries between the low end (7) and the high end (6) of the bidirectional carry bus structure when said data flow component is in nonactive state as determined by the slice function control lines (5) and controlled by the test and control logic unit (17).
Claim 2
Dependent Claim
281 words
A data flow component for use as an element in a processor or microprocessor system comprising a data bus structure (1, 2) for use in transfer of data as input or output to said data flow component, an instruction register (3), an instruction bus (4) for providing instruction to said instruction register, an Arithmetic-Logic Unit (12) for performing arithmetic operations, a pair of operand register A and B (8, 9), a special register Q (10) for use as an extension to a selected one of said operand registers for multiply, divide, and extended shift instructions, a status register (11), a high speed shifter (13), said shifter through selected gating providing a single or multiple shift capability in a single timing interval, a bidirectional carry bus structure (6, 7) for high end and low end carries resulting from arithmetic or shift operations. This data flow component is characterized in that it further comprises: slice function control lines (5) for determining the state of said component and in particular its stand-alone, active or nonactive state; a test and control logic unit (17) connected to the instruction register (3) and to the slice function control lines (5) for acting on instructions related to said data flow component operations and for providing control and test signals pertaining to said data flow component; a carry bypass bus (18) controlled by said test and control logic (17) for providing direct path for carries between the low end (7) and the high end (6) of the bidirectional carry bus structure when said data flow component is in nonactive state as determined by the slice function control lines (5) and controlled by the test and control logic unit (17).
Claim 3
Dependent Claim
178 words
Data flow component according to claim 1, characterized in that it further comprises: means in said test and control logic unit (17) for initiating and controlling at least one of the following classes of operations, each of which is completed as a single combinatorial logic operation during a basic fixed timing interval defined as an instruction cycle: a. all basic ALU functions, such as OR, AND, XOR, addition, subtraction, etc. ; b. divide step wherein each instruction cycle executes one step of a non-restoring algorithm; c. multiply step, wherein each instruction cycle executes a step of a multiply algorithm and one step is required for each two bits of the multiplier; d. single-bit data and status testing; e. comparison testing such as equal, greater than, less than, with both magnitude and algebraic comparison; f. programmable logic gate functions wherein data flow slices are controlled to perform as a single AND, OR, NAND, or NOR gate with program selectable inputs; g. conversions to absolute value, one's complement, or two's complement; and h. increment and decrement with test for zero.
Claim 4
Dependent Claim
139 words
Data flow component according to claim 1 or 2, characterized in that it further comprises: bidirectional multiplex and shift networks (14, 15) interconnected with said B and Q registers (9, 10) and a right shift network (16) interconnected with said ALU (12); and means in said test and control logic unti (17) for initiating at least one of the following classes of operations: i. standard shift functions such as right, left, logical, arithmetic and circular, from one to eight bits per instruction cycle using said high-speed shifter; and j. extended shift operations on the contents of said B and Q registers such as right or left, logical or arithmetic and wherein said multiplex and shift networks for the B and Q registers provide right and left shifts and said right shift network for the ALU provides right shift only.
Claim 5
Dependent Claim
75 words
System for utilizing the data flow component of claims 1, 2 or 3 on a stand-alone basis in a microprocessor or controller system, characterized in that it further comprises: a processor control unit (20) for processing microinstructions; a control memory (21) interconnected with said processor control unit to supply said microinstructions; a read/write memory (22); and interface means (23, 24) for interfacing the aforesaid elements to a master computer and one or more peripheral devices.
Claim 6
Dependent Claim
107 words
System for utilizing the data flow component of claims 1, 2 or 3 on a multiple-component basis such as in a microprogrammable control unit connected for use in conjunction with a high performance central processing unit (CPU), characterized in that it further comprises: a plurality of said data flow components (30-33) interconnected for arithmetic operations, each of said data flow components operating on a separate part of a multi-bit data channel; a control memory (26) serving as a source of microinstructions for a processor control unit (27); and means interconnecting said processor control unit (27) to said data flow components (30-33) for generating and routing of commands.
Claim 7
Dependent Claim
261 words
Multiple-component arrangement for utilizing the data flow component of claims 1, 2, or 3 in a system having a processor control unit, characterized in that it further comprises: a plurality of said data flow components (A.B.C.D) interconnected as data slices for selective arithmetic functions, each of said data flow components including data registers and arithmetic and shift logic, the latter having carry inputs (x) and carry outputs (y); a bidirectional carry bus (40) including both unidirectional and bidirectional transfer capability, said bus being used to transfer shift and arithmetic carry information; an instruction bus (41) for supplying encoded instructions or commands simultaneously to all components; a function control bus (42) including a separate set of encoded control lines interconnected to each component to determine the state of each component in accordance with the following states: a plurality of data buses (43), each of said data flow components serving a predetermined portion or "slice" of each data bus and the number of "slices" determining the total width of the data bus; and a control bus (44) interconnected to each of said components to provide communication between components for control purposes, and also to convey test result information from individual components to said processor control unit, each line of said control bus acting as a "wired-OR" connection between components so that it can be activated by any component and so that its state can be sensed by any component or by the processor control unit whereby a small number of lines serves the control requirements of a large variety of commands or instructions.
Claim 8
Dependent Claim
188 words
Multiple-component arrangement of claim 6, characterized in that it further comprises: control means in said processor control unit for varying the signals on said function control bus (44) in response to special microinstructions from a control storage to establish a variety of operational modes including at least one of the following modes: (1) Combined operation of all data flow components to perform operations on complete operands and to supply complete results to the output data bus which can be gated to internal registers within said individual components or to an external destination; (2) Stand-Alone operation of any selected component wherein said selected component operates on a single byte of data in the same fashion as a data flow element of an 8-bit processor, being totally independent of the state of any other component and in which mode external carry, control, and status signal lines from other slices are ignored; and (3) Subset operation wherein any subset of the components can be operated as a combination to serve as a processor acting on any selected subset of components, inactive components being controlled to act on data as nonactive bytes.
Claim 9
Dependent Claim
32 words
Multiple-component arrangement according to claim 6 or 7 characterized in that said control bus (44) comprises a number of lines that are shared with different functions, depending on the instruction being executed.
Claim 10
Dependent Claim
71 words
Multiple-component arrangement according to claim 8, characterized in that said control lines (44) comprises three lines designated as follows: the designations of said lines being indicative of particular individual functions for which they are used in the majority of the cases, and said lines further being used as a group to convey encoded control information as well as separately to transmit other special control signals unrelated to the designated named functions.
Claim 11
Dependent Claim
176 words
Multiple-component arrangement according to claim 9, wherein efficient communication is established, characterized in that it further comprises: means interconnecting said Test Result Indicator line among said components to convey control information between components; such means operable in test instructions, such as bit tests, comparison tests, and increment or decrement with a test for zero for controlling the Test Result Indicator line for use to signal a true of false result indication to the processor control unit and wherein the Test Result Indicator line is activated by any components depending on the location of the tested condition; means operable in a test for zero for controlling said Zero Test Indicator line to convey the aggregate result to the Highest Active Byte where it is outputted to said Test Result Indicator line; and means for controlling said Test Result Indicator, Even Test Indicator and Zero Test Indicator lines as a path for encoded control information, generated by one or more components to be used in controlling the actions of other components in accordance with a selected control algorithm.
Claim 12
Dependent Claim
71 words
Multiple-component arrangement according to claim 10 characterized in that all active components receive and execute the same instruction on different bytes of the operand, such as in a Convert to Absolute Value instruction, wherein the conditions or results of actions in one component may affect the actions of other components, and wherein the respective Test Result Indicator, Even Test Indicator, and Zero Test Indicator lines convey selected information to the components.
Claim 13
Dependent Claim
138 words
Multiple-component arrangement according to claim 10, characterized in that it further comprises: means to execute an instruction such as a Divide Step instruction, each instruction cycle executing one step of a nonrestoring division operation by using control lines as follows: A conditional addition or substraction is performed by every component depending on the state of the negative indicator set in the Highest Active Byte as a result of the preceding step and the state of the indicator being conveyed via said Test Result Indicator line; and the Least Significant Bit of Q, located in the Lowest Byte, is set according to the sign of the result of the current operation, addition or subtraction, and the state of the sign bit being transferred from the Highest Active Byte to the Lowest Active Byte via said Even Test Indicator line.
Claim 14
Dependent Claim
71 words
Multiple-component arrangement according to claim 10, characterized in that it further comprises: means to execute an instruction such as a Multiply Step instruction wherein during each Multiply Step the actions of all components vary in accordance with a predetermined truth table; wherein special status information is located in the same byte of a selected register; and wherein special status information is transferred to said same byte by means of control lines.
Claim 15
Dependent Claim
207 words
Multiple-component arrangement according to claim 13, characterized in that the Multiply Step operation starts with the multiplicand in the A register and the multipler in the Q register, the product is developed in the B and Q registers by a sequence of conditional arithmetic (addition or substraction) and shift operations and the conditions that govern the types of operations performed by each of a sequence of identical Multiply Step instructions are supplied by the two least significant bits of the Q register, which are designated Q6 and Q7 of the Lowest Active Byte and a special status bit, which acts as a low-end extension of the 0 register during right-shift operations, the special status bit being referred to as Q8, wherein during each multiply step the actions of all slices vary in accordance with the following truth table: wherein at the end of each step the Q register is shifted right two positions and the two vacated most-significant-bit positions are filled by carries from the B register and ALU shift networks via lines in the carry bus; and further comprising: means for controlling the Test Result Indicator, Even Test Indicator and Zero Test Indicator Lines, respectively, to supply the state of selected bit positions to all components.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.