Semiconductor device especially a memory cell in V-MOS technology

Claim 2

Semiconductor device especially a memory cell comprising a semiconductor substrate (10, 14) having at least one recess (18) provided in a surface thereof, and a first dielectrically insulated conductive layer (22) on said substrate (10, 1.4) having at least a portion (22) of which extends into said recess (18), characterized in that said first conductive layer (22) having at least a portion of at least one edge thereof terminating within said recess (18) below the level of the surface of said substrate (10, 14), and a second conductive layer (34) overlying at least a portion of said first conductive layer (22) which extends into said recess (18), said second conductive layer (34) making physical contact (30, 32) to said substrate (10, 14) within said recess (18) below the level of the surface of said substrate (10, 14).

Claim 3

Semiconductor device in accordance with claim 1 characterized in that said semiconductor substrate (10, 14) is of a first conductivity type (P, P+) and that at least one first region (30, 32) of second conductivity type (N+) is provided in said recess (18) below the level of the surface of said substrate which is contacted by said second conductive layer (34).

Claim 4

Semiconductor device in accordance with claim 1 or 2 further including a second region (12) of second conductivity type (N+) provided in said recess (18) said second region (10) being spaced from said first region (30, 32) and lying below said portion of said first conductive layer (22) which extends into said recess (18).

Claim 5

Semiconductor device in accordance with one of the preceeding claims characterized in that said recess (18) is V-shaped.

Claim 6

V-MOSFET semiconductor memory cell comprising a semiconductor substrate (10, 14) of. a first conductivity type (P) having a V-shaped recess (18) formed in a first surface thereof, a charge storage region (12) formed in said substrate (10, 14) in contact with the apex of said V-shaped recess (18), and a first dielectrically insulated conductive word line electrode (22) passing over said recess (18) characterized in that said electrode (22) having two parallel edges being defined within said recess (10) below said first surface of said substrate, in that first and second regions (30, 32) of second conductivity type (N+) are formed in said recess (18), said regions (30, 32) being substantially defined by the surfaces of said V-shaped recess at their inter-. section with said first surface of said substrate and by a respective edge of said word line electrode (22); and in that a conductive bit line electrode (34) substantially orthogonal to said word line electrode (22) is provided, said bit line electrode (34) passing over said word line electrode. (22) and making contact to both of said first and second regions (34, 32) of second conductivity type within said recess below said surface of said substrate.

Claim 7

V-MOSFET semiconductor memory cell comprising a semiconductor substrate (10, 14) of. a first conductivity type (P) having a V-shaped recess (18) formed in a first surface thereof, a charge storage region (12) formed in said substrate (10, 14) in contact with the apex of said V-shaped recess (18), and a first dielectrically insulated conductive word line electrode (22) passing over said recess (18) characterized in that said electrode (22) having two parallel edges being defined within said recess (10) below said first surface of said substrate, in that first and second regions (30, 32) of second conductivity type (N+) are formed in said recess (18), said regions (30, 32) being substantially defined by the surfaces of said V-shaped recess at their inter-. section with said first surface of said substrate and by a respective edge of said word line electrode (22); and in that a conductive bit line electrode (34) substantially orthogonal to said word line electrode (22) is provided, said bit line electrode (34) passing over said word line electrode. (22) and making contact to both of said first and second regions (34, 32) of second conductivity type within said recess below said surface of said substrate.

Claim 8

V-MOSFET semiconductor memory cell in accordance with claim 5, characterized in that said charge storage region (12) comprises a third region of second conductivity type.

Claim 9

Method of forming a semiconductor device in accordance with one of the preceeding claims comprising the steps of: providing a semiconductor substrate of a first conductivity type, , forming a recess in a surface of said substrate, forming a first insulating layer on exposed surfaces of said recess, selectively forming a dielectrically insulated first layer of conductive electrode material on said first insulating layer, a portion of the edges of said first layer of conductive electrode material being formed within said recess, removing portions of said insulating layer exposed within said recess to expose portions of said substrate, and forming a second layer of conductive electrode material over said insulated first layer of conductive electrode material and in physical contact with said exposed portions of said substrate in said recess.

Claim 10

Method in accordance with claim 7, characterized in that following the step of removing portions of said first insulating layer there is provided a step of forming second conductivity type regions in exposed portions of said substrate in said recess.

Claim 11

Method in accordance with claim 7 or 8, characterized in that prior to selectively forming the dielectrically insulated first layer of conductive electrode material there is provided a charge storage region in said substrate under and in contact with said recess.

Claim 12

Method in accordance with claim 8 or 9, characterized in that said second conductivity type regions and said charge storage region are formed by ion implanting a conductivity determining impurity into said substrate.

Claim 13

Method of making a V-MOS memory cell comprising the steps of: providing a semiconductor substrate of a first conductivity type, providing a first second-conductivity type region in a surface of said substrate, growing an epitaxial layer of semiconductor material over said substrate and said second conductivity type region, providing a dielectric masking material over said epitaxial layer, selectively etching a substantially square hole in said masking layer in a position directly over said first second-conductivity type region, selectively etching the exposed portion of said substrate to form a recess in said substrate, said recess terminating within said first second-conductivity type region, characterized by providing a first insulating layer over exposed surfaces of said recess, depositing a first conductive layer over said substrate including said recess, depositing a second insulating layer over said first conductive layer, selectively removing portions of said second insulating layer and said first conductive layer by providing a self-leveling masking layer over said substrate, uniformly removing said self-leveling masking material until portions of said material remain only in said recess and thereafter selectively etching said second insulating layer and said first conductive layer, forming a dielectric insulating layer on exposed areas of said first conductive layer, forming exposed second and third regions of second conductivity type within said recess and adjacent to said insulated first conductive layer remaining in said recess, and depositing a second conductive layer over said substrate and within said recess to provide contact to each of said exposed second and third regions.

Claim 14

Method of making a V-MOS memory cell comprising the steps of: providing a semiconductor substrate of a first conductivity type, providing a first second-conductivity type region in a surface of said substrate, growing an epitaxial layer of semiconductor material over said substrate and said second conductivity type region, providing a dielectric masking material over said epitaxial layer, selectively etching a substantially square hole in said masking layer in a position directly over said first second-conductivity type region, selectively etching the exposed portion of said substrate to form a recess in said substrate, said recess terminating within said first second-conductivity type region, characterized by providing a first insulating layer over exposed surfaces of said recess, depositing a first conductive layer over said substrate including said recess, depositing a second insulating layer over said first conductive layer, selectively removing portions of said second insulating layer and said first conductive layer by providing a self-leveling masking layer over said substrate, uniformly removing said self-leveling masking material until portions of said material remain only in said recess and thereafter selectively etching said second insulating layer and said first conductive layer, forming a dielectric insulating layer on exposed areas of said first conductive layer, forming exposed second and third regions of second conductivity type within said recess and adjacent to said insulated first conductive layer remaining in said recess, and depositing a second conductive layer over said substrate and within said recess to provide contact to each of said exposed second and third regions.

Claim 15

Method in accordance with claim 11, characterized in that an anisotropic etchant is used to etch said exposed portion of said substrate and in that said substrate is 100 oriented silicon semiconductor material.